Integrated Process Flow Research Articles

Recent Technology Developments in Textile Industry

Landscape in textiles for India is changing greatly due to technological development. There are huge numbers of mills in India that have integrated process flow right from spinning operation to apparel manufacturing. Digital transformation is bridging the gap between technology and textiles. High-fibre fabrics production is capable only with the implementation of modern solutions. Technology in textile industry has improved processes and making fabrics production more efficiently. Recent developments in technology in textiles show that textile and fashion segment will continue to evolve with the continuous innovations. Technology developed to enable vibrant imaging on fabrics and alterations to be done with a simple click on mouse. With the latest technological developments and innovations, the apparel industry is undergoing with interested changes. In the modern textile designs, digital photo types are used as an essential tool. Varieties of IoT sensors are used to collect persons’ biometric data for the purpose of effective health and activity monitoring.

Heterogeneous integration of Si photodiodes on silicon nitride for near-visible light detection.

Silicon nitride (SiN) is used extensively to complement the standard silicon photonics portfolio. However, thus far demonstrated light sources and detectors on SiN have predominantly focused on telecommunication wavelengths. Yet, to unlock the full potential of SiN, integrated photodetectors for wavelengths below 850 nm are essential to serve applications such as biosensing, imaging, and quantum photonics. Here, we report the first, to the best of our knowledge, microtransfer printed Si p-i-n photodiodes on a commercially available SiN platform to target wavelengths <850 nm. A novel heterogeneous integration process flow was developed to offer a high microtransfer printing yield. Moreover, these devices are fabricated with CMOS compatible and wafer-scale technology.

Laser Debonding of Ultrathin Wafers and Packages: A Technology for the New Generation of Electronic Devices

The continuous shrinkage of the device wafers thickness is driving the current mature debonding technologies to their limits. The challenging form factor demands for memory (≤ 30 µm) or new generations of power devices applications are just two examples for the need of lowering the device thickness.Slide-off as well as mechanical debonding are methods currently in use in high volume production, but these two technologies are not capable to support the new requirements in terms of thermal and mechanical stability, handling, throughput (affecting the cost of ownership - CoO), and process margin. Therefore, device manufactures are looking for a more versatile, universal debonding technology. State of the art UV laser debonding is a very promising candidate which can help bringing the required process margin and flexibility. By combining laser debonding and thermoset materials with a high thermal budget the process window can be significantly enhanced.Most of the thermoset materials of interest which are used to form a bond and to embed the device topography cannot be stimulated directly with UV light. In order to enable a debonding process for these materials, an additional layer is commonly deposited on the carrier. The post bond uniformity (quantified typically by the total thickness variation - TTV) of the used bulk layer of thermoset adhesive has to be very well controlled in order to enable a defect free thinning of the device wafer: this becomes crucial particularly when the final device layer has to be thinned down below 10 µm. Besides the optimization of the bond layer thickness uniformity, suitable carriers for different devices and applications were evaluated. Due to the significant variety of the available glass carriers, a customized temporary bonding process can be developed by selecting the most appropriate adhesive and carrier combinations suitable even for very challenging substrates, like reconstituted wafers.Reconstituted wafers consist of a number of different layers and materials with different thermal expansion coefficients, which makes the stress management and the handling of such substrates extremely difficult. However, the choice of the suitable carrier enables the processing independent of the chosen integration process flow (RDL first; Chip first). Even a carrier flip flop to enable the processing of the back side of the very thin package is possible and this is enabling the creation of ultra-thin and smart packages.The scope of the current work was to address the post bond adhesive thickness uniformity as well as the stress management. Experimental results will be presented for the process optimization: figure 1 shows two bow measurement results for two different carrier materials and figure 2 shows an example of post-bonding thermoset adhesive uniformity measurement Figure 1

Fabrication Steps and Thermal Modeling of Three-Dimensional Asynchronous Field Programmable Gate Array (3D-AFPGA) With Through Silicon Via and Copper Pillar Bonding Approach

Abstract This work will specifically detail the development of a processing and fabrication route for a three-dimensional asynchronous field-programmable gate array (3D-AFPGA) design based on an extension of pre-existing two-dimensional-field-programmable gate array (2D-FPGA) tile designs. The periodic nature of FPGAs permits the use of an alternative approach, whereby the design entails splitting the FPGA design along tile borders and inserting through silicon vias (TSVs) at regular spatial intervals. This serves to enable true 3D performance (i.e., full 3D signal routing) while leaving most of the 2D circuit layouts intact. 3D signal buffers are inserted to handle communication between vertical and adjacent neighbors. For this approach, the density of vertical interconnections was shown to be determined by the size of the bond pads used for tier–tier communications and bonding. As a consequence, reducing bond pad dimensions from 25 μm to 15 μm, or 10 μm, bond pads are preferred to increase the connectivity between layers. A 3D-AFPGA mockup test structure was then proposed for completing development and exercising the 3D integration process flows. This mockup test structure consists of a three-tier demonstration vehicle consisting of a chip-to-wafer and a subsequent chip-to-chip bond. Besides, an alternate copper bonding approach using pillars was explored. Although the intended application is for the 3D integration process compatible with the 3D AFPGA design, the test structure was also designed to be generally applicable to various applications for 3D integration. Because of the importance of thermal management of 3D-AFPGA, it is important to predict the temperature distribution and avoid the maximum junction temperature. The numerical thermal modeling for predicting the equivalent thermal conductivity in every layer and the 3D temperature distribution in the 3D-AFPGA are developed and discussed as well.

Process Modules for High-Density Interconnects in Panel-Level Packaging

Advanced packaging technologies like wafer-level fan-out and 3-D system-in-package (3-D SIP) are rapidly penetrating the market of electronic components. For cost reduction, one approach is the migration of processes from wafer to panel format, called panel-level packaging (PLP). In a consortium of partners from industry and research, advanced technologies for PLP are developed. The project aims for an integrated process flow for 3-D SIPs with chips embedded into an organic laminate matrix. At first, 6 mm $\times 6$ mm chips (100 $\mu \text{m}$ thickness) with Cu bumps (25- $\mu \text{m}$ height, 110- $\mu \text{m}$ pitch) are placed into cavities of a printed circuit board (PCB) core layer. They are embedded by vacuum lamination of thin organic films. The core is equipped with fiducials for local alignment and provides handling robustness. Developments aim for a final panel size of 600 mm $\times600$ mm (here 227 mm $\times305$ mm demonstrated). Onto the contact side of embedded chips, a 25- $\mu \text{m}$ dielectric film is applied. The copper bumps are subsequently opened by plasma etching. By sputtering and electroplating of Cu, electrical contacts to the chips are formed without via opening. High-aspect-ratio vias as an element for vertical interconnects are formed by UV laser drilling. At via diameters of 17 $\mu \text{m}$ , a drill hole depth of 74 $\mu \text{m}$ was achieved (aspect ratio 4.4:1). Using a newly developed electrolyte, microvia filling was achieved for aspect ratios up to 4:1. With a newly developed direct imaging (DI) machine, 4- $\mu \text{m}$ structures in a 7- $\mu \text{m}$ dry film photoresist are formed. Adaptive imaging of a redistribution layer was realized.

Foundry Photonic Process Extension With Bandgap Tuning Using Selective Area Growth

The extension of a photonic integrated circuit foundry process flow is proposed by integrating selective area growth to enable bandgap tuning for each individual active building block. The process adaptations and the impact on performance are reviewed in terms of morphology requirements and topology reduction. This platform extension enables bandgap tuning for a set of active devices to cover the wavelength range from 1453 to 1651 nm. Integration is demonstrated in combination with active–passive butt-joint technology to create the most comprehensive range of generic building blocks. Performance and limitations of the range of achievable band edges within the same monolithic wafer are studied for amplifiers and extended cavity lasers.

Metal barrier induced damage in self-assembly based organosilica low-k dielectrics and its reduction by organic template residues

This study describes the damage caused by physical vapor deposition of TaN/Ta barriers on porous self-assembled organosilica low-k dielectrics for IC applications. It is demonstrated that the ion bombardment associated with TaN layer sputtering strongly influences the metal species in-diffusion and modifies the bulk dielectric and pore sealing characteristics. The modulation of the pore structure via controlled decomposition of the organic template, prior to the barrier deposition step, allows to mitigate this damage. The reduction of open porosity, from nominal 39% down to 26%, is realized by partial retention of the sacrificial organic porogen phase in the pores of the low-k dielectric, resulting in the suppression of deep Ta penetration and in the recovery of pore sealing. This approach is successfully tested in a 45 nm half-pitch damascene vehicle. The compatibility of the organic template residues with the subsequent steps of the interconnects integration process flow, such as hard-mask deposition and patterning, are discussed.

Development of High Density RDL Technologies for Panel Level Processing

Advanced packaging technologies like wafer-level fan-out and 3D System-in-Packages (SIPs) are rapidly penetrating the market of electronic components. A recent trend to reduce cost is the extension of processes to large manufacturing formats, called Panel Level Packaging (PLP). In a consortium of German partners from industry and research advanced technologies for PLP are developed. The project aims for an integrated process flow for SIPs with chips embedded into an organic laminate matrix. At first dies with Cu pillar structures are placed into openings of a laminate frame layer with very low coefficient of thermal expansion (CTE). They are embedded by vacuum lamination of thin organic films, filling the very small gap down to 15 μm between chips and frame. The frame provides alignment marks for a local registration of following processes. The ridged frame limits die shift during embedding and gives a remarkable handling robustness. Developments are initially performed on a 305×256mm2 panel format, aiming for a final size of 610×615 mm2. On the top side of embedded chips, a 20μm dielectric film is applied. The goal is to avoid additional via formation and to realize a direct connection between the Cu pillar of the die and the RDL The RDL formation is based on semi-additive processing. Therefore a Ti or TiW barrier and Cu seed layer is sputtered. Subsequently a 7μm photoresist is applied and exposed by a newly developed Direct Imaging (DI) system. Lines and spaces of 4μm were achieved with high yield. In the following, Cu is simultaneously electroplated for the via contacts and interconnects traces. Finally, the photo resist is stripped and the TiW barrier and Cu seed layers are etched. The goal of the development is to provide a technology for a high-density RDL formation on large panel sizes. The paper will discuss the new developments in detail, e.g. the influence of most significant process parameters, like lithographical resolution, minimum via diameter and the placement and alignment accuracy on overall process yield.

Epitaxial Bonding and Transfer Processes for Large-Scale Heterogeneously Integrated Electronic-Photonic Circuitry

A process flow for the heterogeneous integration of III-V epitaxial material onto a silicon host wafer using CMOS-compatible materials and methods toward the goal of forming electronic-photonic circuitry is presented. Epitaxial structures for compound-semiconductor-based transistors are assembled on a silicon carrier wafer using a commercially-available polymer and then formed into distinct patterns for scalable processing. A CMOS-compatible metallization process is performed on the back side collector terminal of the aligned epitaxial structures, followed by a metal-eutectic bonding process that transfers the wafer-scale array of III-V material onto a separate silicon host wafer allowing the fabrication of both electronic and photonic devices on a single wafer. Characterization of the epitaxial bonding and transfer is performed to ensure material alignment is maintained without additional tooling and that the interconnect layer established between III-V collector and silicon host wafer performs as an ohmic contact, thermal path, and mechanical bond compatible with back-end-of-line (BEOL) integrated circuit processing. These processes are shown for GaAs-based light-emitting transistor (LET) epitaxial material to demonstrate that subsequent photonic devices and systems may be patterned into the integrated material allowing a direct electrical interconnect to embedded CMOS-based electronic systems for new functionalities as electronic-photonic integrated circuitry.

New insights on SOI Tunnel FETs with low-temperature process flow for CoolCube™ integration

This paper reports the fabrication and electrical characterization of planar SOI Tunnel FETs (TFETs) made using a Low-Temperature (LT) process designed for 3D sequential integration. These proof-of-concept TFETs feature junctions obtained by Solid Phase Epitaxy Regrowth (SPER). Their electrical behavior is analyzed and compared to reference samples (regular process using High-Temperature junction formation, HT). Dual ID-VDS measurements verify that the TFET structures present Band-to-Band tunnelling (BTBT) carrier injection and not Schottky Barrier tunnelling. P-mode operating LT TFETs deliver an ON state current similar to that of the HT reference, opening the door towards optimized devices operating with very low threshold voltage VTH and low supply voltage VDD.

Proposed DSO ancillary service processes considering smart grid requirements

The role of distribution system operator (DSO) in a smart grid environment includes five services, namely, flexibility services, infrastructure provision for electric vehicles, energy efficiency services, ownership and management of metering equipment, and data handling. An important role of DSOs in a smart grid environment is the flexibility services, which are also required by transmission system operator (TSO), suppliers and balancing responsible parties. With different objectives this may, at times, lead to conflicting interests. To safeguard the proper functioning of the energy system, a form of coordination will be required to address and resolve these conflicting interests. A proposed DSO ancillary service processes are identified considering smart grid requirements. The intelligence of the smart grid is critically reliant on geospatial data to represent and track numerous devices' locations within the connected model of the distribution system. Geographical information system is an essential tool for handling the proposed DSO ancillary service processes in an efficient way. An integrated process flow diagram for the proposed DSO ancillary services together with TSO ancillary services is developed.

Nanoparticle assembly enabled by EHD-printed monolayers

Augmenting existing devices and structures at the nanoscale with unique functionalities is an exciting prospect. So is the ability to eventually enable at the nanoscale, a version of rapid prototyping via additive nanomanufacturing. Achieving this requires a step-up in manufacturing for industrial use of these devices through fast, inexpensive prototyping with nanoscale precision. In this paper, we combine two very promising techniques—self-assembly and printing—to achieve additively nanomanufactured structures. We start by showing that monolayers can drive the assembly of nanoparticles into pre-defined patterns with single-particle resolution; then crucially we demonstrate for the first time that molecular monolayers can be printed using electrohydrodynamic (EHD)-jet printing. The functionality and resolution of such printed monolayers then drives the self-assembly of nanoparticles, demonstrating the integration of EHD with self-assembly. This shows that such process combinations can lead towards more integrated process flows in nanomanufacturing. Furthermore, in-process metrology is a key requirement for any large-scale nanomanufacturing, and we show that Dual-Harmonic Kelvin Probe Microscopy provides a robust metrology technique to characterising these patterned structures through the convolution of geometrical and environmental constraints. These represent a first step toward combining different additive nanomanufacturing techniques and metrology techniques that could in future provide additively nanomanufactured devices and structures.

Combined Injection Molding Technology for Dynamically Stressed Multi-Material Coupling Elements

The manufacturing of high load components in automotive and mechanical engineering demands for an increased usage of combined plastics processing procedures. In practice, full plastic hybrid components are produced in a series of individual processes such as thermoforming or injection molding. The constructive implementation has often only material-substituting character wherein the high potential for lightweight anisotropic fiber composites is exploited only to a limited extent. Based on the application of a coupling brace in a vehicle, a new component design for function-integrated interface elements is enabled by an integrated injection molding technology. The targeted transfer of high local stresses by load-bearing insert elements regarding contoured metal sheets or Fiber Reinforced Thermoplastic Composites (TP-FRC) semi-finished products with endless fiber reinforcement enables efficient dimensioning of components. This fusion of technologies to a Multi Material Design (MMD) form the basis for novel weight-optimized, as well as cost-effective applications and lead to a high bending stiffness and high strength of structures. The composite strength of MMD components is increased by a variation and optimization of the thermoplastic/TP-FRC respectively thermoplastic/metal-interfaces. This objective will be achieved by highly efficient and integrated process flows and by the new entire construction of the component.

Impact of surface preparation for n-type Si:P and p-type SiGe:B semiconductors on low resistance silicide contacts

In our study, we evaluate effective silicon and germanium oxide reduction by two surface treatments to achieve low contact resistivity at the semiconductor/metal interface. These chemistries, one alkaline and the other an acidic fluorine-based treatment, were utilized on epitaxial n-type Si:P and p-type Si1−xGex:B (x=0.47) substrates to isolate any unique effects that may be present on doped, n-type and p-type semiconductor surfaces. To mimic plasma damage and surface conditions in an integrated process flow for actual logic devices, X-ray photoemission spectroscopy (XPS) characterization was performed on simplified blanket films after NF3-based gas cluster ion beam (GCIB) exposure and subsequent aqueous treatments. Si:P and SiGe:B surfaces both demonstrated an increase in SiO2 concentration after GCIB exposure, with SiGe:B surfaces showing a preferential SiO2 surface oxidation. Subsequent acidic treatment showed reduction in SiO2 concentration on both epitaxial surfaces, with the alkaline (basic) treatment showing little change in surface composition. Electrical characterization on simplified contact structures showed a benefit in contact resistivity of 15–23% in Si:P and 10–13% in SiGe:B for the chemistries evaluated.

Embedded RDL formation in Non-Photo Polymers using Excimer Laser Ablation

Abstract The continuous trend towards miniaturization, increasing performance and mobility of electronic devices drives interconnect density and integration, not only at the chip level, but also at interposer and package level. Silicon interposers coming from wafer foundries using back end of line (BEOL) redistribution layer (RDL) processes have been introduced successfully. However, there is a continuing need for low cost interposers based on large organic or glass panels. While traditional organic flip-chip substrates using semi-additive processes (SAP) have not been able to scale to ultra-fine RDL pitches, photo-sensitive spin-on dielectrics and RDL processes used for wafer level packaging do not sufficiently address the cost reduction need, This paper presents the latest results from cost effective and innovative package RDL processes using excimer laser ablation, to meet the market's most stringent requirements. To enable panel and wafer based interposers to reduce RDL cost and scale interconnect pitch to 40um and below, excimer laser ablation is introduced as a direct patterning process that uses proven industrialized excimer laser sources to emit high-energy pulses at short wavelengths to remove polymer materials with high precision and high throughput. The combination of a high-power excimer laser source, large-field laser mask and precision projection optics enables the accurate replication and placement of fine resolution circuit patterns without the need for any wet-processing. In addition, with excimer laser patterning technology the industry gains a much wider choice of dielectric materials (photo and non-photo) to help achieve further reductions in manufacturing costs as well as enhancements in interposer and package performance. In this paper, we propose new process that uses excimer laser ablation to integrate via and RDL traces in one patterning process step, followed by seed layer deposition, plating and planarization steps. A new integration process flow is proposed, and its technical robustness and commercial advantages have been demonstrated. The capability of this excimer laser process to extend the current material portfolio to non-photo materials will be discussed, and its commercial benefits as compared to the current process of record (POR) will be highlighted.

(Invited) Novel Integrated Circuit Platforms Employing Monolithic Silicon CMOS + GaN Devices

We describe the research results produced from our focus on integrating GaN HEMTs and LEDs into silicon CMOS integrated circuits. Although current component markets are driving most GaN HEMT development, we have undertaken an innovation path in which the value of an integrated GaN device in a silicon design environment is the driver for materials and device development. Specifically, our integrated process flow involving foundry production of front and back end standard CMOS processes demands certain GaN epitaxial and material constraints that are different than constraints on non-integrated devices. We report on 200 mm GaN-on-Si 725 um thick engineered substrates formed through a combination of MOCVD and wafer bonding processes. Our optimized 200 mm GaN-on-Si (111) epitaxial wafers have bow values < 30 um, with total III-N film thicknesses of 2.7 um including a 1.5 um capping GaN layer. XRD FWHM values of 400 and 380 arcsec for (002) and (102) reflections indicate TDD of approximately 4e8 cm-2. CMOS-compatible GaN HEMTs demonstrated on these wafers have achieved 2DEG mobilities of ~1200 cm2/Vs and sheet carrier densities of 1-2e13 cm-2, with Id, max values of 700 mA/mm and 25 GHz fT, fmax for Lg = 0.25 um. High quality InGaN/GaN MQW LEDs emitting at 450 nm with total III-N stack thickness of 3.7 um have also been demonstrated. Central emission wavelength standard deviation of < 2 nm was achieved across the entire 200 mm, wafer, and typical devices exhibited turn-on at ~2.5 V with diode ideality factor of 2.8. We have developed wafer engineering techniques such as edge encapsulation and substrate replacement to address wafer fragility issues typically associated with GaN on SEMI-spec 725 um Si wafers. This also leads new wafer/device platforms such as GaN-OI and CMOS + GaN that will open new avenues in device performance and integration of III-N with Si CMOS.

(Invited) Novel Integrated Circuit Platforms Employing Monolithic Silicon CMOS + GaN Devices

We describe the research results produced from our focus on integrating GaN HEMTs and LEDs into silicon CMOS integrated circuits. Although current component markets are driving most GaN HEMT development, we have undertaken an innovation path in which the value of an integrated GaN device in a silicon design environment is the driver for materials and device development. Our integrated process flow employs standard foundry production of front and back end CMOS. Such constraints demand certain GaN epitaxial and material criterion that is different than those on non-integrated devices. We report on 200 mm GaN-on-Si 725 um thick engineered substrates formed through a combination of MOCVD and wafer bonding processes. We have developed wafer engineering techniques such as edge encapsulation and substrate replacement to address wafer fragility issues typically associated with GaN on SEMI-spec 725 um Si wafers. This also leads new wafer/device platforms such as GaN-OI and CMOS + GaN that will open new avenues in device performance and integration of III-N with Si CMOS.

Discovering Context-Specific Integration Practices for Integrating NEPA into Statewide and Metropolitan Project Planning Processes

AbstractWhen the National Environmental Policy Act (NEPA) process and the transportation project planning process are not streamlined, the NEPA process may lead to duplication of work and project delays. This paper presents research work in discovering state-suitable integration practices for integrating NEPA into statewide and metropolitan transportation project planning processes for the state of Illinois. The discovery of practices was based on an analytical review of existing integration guidelines and efforts in other states and using a survey of experts from relevant federal, state, and metropolitan planning, regulatory, and resource agencies. Two types of integration practices were identified: process-oriented and collaboration-oriented integration practices. The selected practices were integrated into existing transportation project planning processes and formalized into an integrated process flow with detailed implementation guidance. The integrated process was validated through a second expert s...

Copper electroplating technique for efficient manufacturing of low-cost silicon interposers

Through-silicon via (TSV) technology is the heart of 3D integration technology. An approach was proposed to simplify the integrated process flows. Dry film photoresist was introduced in the through via filling process. Cu-TSVs and Cu-pads were formed simultaneously through the electroplating process, which diminished the interface between Cu-TSVs and Cu-pads. This approach simplified the integrated process flows, enhanced the reliability, and lowered the costs dramatically compared with the most preferred TSV fabrication method in the industry today, which would have a broad application in the 3D integration industry.

Multilayer Silicon Nitride-on-Silicon Integrated Photonic Platforms and Devices

We review and present additional results from our work on multilayer silicon nitride (SiN) on silicon-on-insulator (SOI) integrated photonic platforms over the telecommunication wavelength bands near 1550 and 1310 nm. SiN-on-SOI platforms open the possibility for passive optical functionalities implemented in the SiN layer to be combined with active functionalities in the SOI. SiN layers can be integrated onto SOI using a front-end or back-end of line integration process flow. These photonic platforms support low-loss SiN waveguides, low-loss and low-crosstalk waveguide crossings, and low-loss interlayer transitions using adiabatic tapers. Novel ultra-broadband and efficient grating couplers as well as polarization management devices are enabled by the close coupling between the silicon and SiN layers.