Abstract
The continuous shrinkage of the device wafers thickness is driving the current mature debonding technologies to their limits. The challenging form factor demands for memory (≤ 30 µm) or new generations of power devices applications are just two examples for the need of lowering the device thickness.Slide-off as well as mechanical debonding are methods currently in use in high volume production, but these two technologies are not capable to support the new requirements in terms of thermal and mechanical stability, handling, throughput (affecting the cost of ownership - CoO), and process margin. Therefore, device manufactures are looking for a more versatile, universal debonding technology. State of the art UV laser debonding is a very promising candidate which can help bringing the required process margin and flexibility. By combining laser debonding and thermoset materials with a high thermal budget the process window can be significantly enhanced.Most of the thermoset materials of interest which are used to form a bond and to embed the device topography cannot be stimulated directly with UV light. In order to enable a debonding process for these materials, an additional layer is commonly deposited on the carrier. The post bond uniformity (quantified typically by the total thickness variation - TTV) of the used bulk layer of thermoset adhesive has to be very well controlled in order to enable a defect free thinning of the device wafer: this becomes crucial particularly when the final device layer has to be thinned down below 10 µm. Besides the optimization of the bond layer thickness uniformity, suitable carriers for different devices and applications were evaluated. Due to the significant variety of the available glass carriers, a customized temporary bonding process can be developed by selecting the most appropriate adhesive and carrier combinations suitable even for very challenging substrates, like reconstituted wafers.Reconstituted wafers consist of a number of different layers and materials with different thermal expansion coefficients, which makes the stress management and the handling of such substrates extremely difficult. However, the choice of the suitable carrier enables the processing independent of the chosen integration process flow (RDL first; Chip first). Even a carrier flip flop to enable the processing of the back side of the very thin package is possible and this is enabling the creation of ultra-thin and smart packages.The scope of the current work was to address the post bond adhesive thickness uniformity as well as the stress management. Experimental results will be presented for the process optimization: figure 1 shows two bow measurement results for two different carrier materials and figure 2 shows an example of post-bonding thermoset adhesive uniformity measurement Figure 1
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