Integrated Gate Driver Research Articles

Review of Integrated Gate Driver Circuits in Active Matrix Thin-Film Transistor Display Panels.

Many advanced technologies have been employed in high-performance active matrix displays, including liquid crystal displays, organic light-emitting diode displays, and micro-light-emitting diode displays. On the other side, there exists a strong demand for cost reduction, and it is one of the low-cost schemes for integrating the driver circuit in a panel based on thin-film transistor technologies. This paper reviews the overall concept, operation principles, and various circuit approaches in shift registers for scanning pulse generation. In addition, it deals with the implementation of additional functionalities in gate drivers to support pixel compensation, multi-line driving, in-cell capacitive touch screen, pixel sensing, and adaptive scanning region control.

Dual-bootstrapping gate driver circuit design using IGZO TFTs

To promote the integration of thin-film transistor (TFT) gate driver circuit technology into high-resolution large-size display application with narrow bezel, achieving high speed is a critical challenge. This paper proposed a dual-bootstrapping TFT integrated gate driver circuit for large-size display. The over-drive voltage of the driving TFT was increased both at the rising and falling edges of the output waveforms. To validate the circuit feasibility, the proposed circuit was fabricated using amorphous indium-gallium-zinc-oxide (a-IGZO) TFT technology and measured in terms of transient response with cascaded stages and reliability tests over long operating time. Compared to conventional approaches, the proposed gate driver demonstrates a 39 % reduction in the falling time as well as compact layout. Therefore, the proposed gate driver schematic is well-suited for large-size display applications that involves heavy resistance–capacitance (RC) loadings and require high resolution above 8 K.

GaN HEMT and Air Core Magnetics based Power Converters Evaluations at Cryogenic Temperature

Cryogenic power electronics is both advantageous and indispensable in many applications, like deep space probe, military electric vehicle, magnetic resonance imaging etc. Among different semiconductors, the gallium nitride (GaN) high electron mobility transistor (HEMT) is the most promising candidate for cryogenic applications with significant conduction loss and switching loss reductions. Moreover, there is no carrier freeze out effect for the GaN HEMTs, which is applicable in extreme low temperature operating conditions. In this work, the efficiency of GaN HEMTs based power converters with different power levels (from several Watts to several kiloWatts) are evaluated at cryogenic temperature. Three different commercial GaN HEMTs are used in these power converters, including the Texas Instruments LMG5200 80 V GaN half-bridge power stage with integrated gate driver, the GaN Systems 650 V bottomcooled GaN HEMT GS66516B, and the 650 V top-cooled GaN HEMT GS66516T from GaN Systems. Moreover, two different cryogenic power converter evaluation methods (cryogenic chamber and liquid nitrogen channeled through cold plate) are investigated. Three of these power converters are evaluated by using a cryogenic chamber and such that the converter operating environment temperature can be regulated. One of the power converters is evaluated by using liquid nitrogen (LN2) channeled through a cold plate, where the gate driver can be designed to operate at non-cryogenic temperatures to ensure the safe operation of the system. Due to the degraded performance of conventional magnetic components, air core magnetics are used in these power converters to improve the converter efficiency. Efficiency improvements at cryogenic temperature are observed for all the GaN HEMTs and air core magnetics based power converters, which are promising for cryogenic power electronics applications.

High-speed, low-voltage, small-pitch and robust OTFT-based integrated gate driver for active-matrix displays

We design and fabricate a high-speed, low-voltage, small-pitch, and robust integrated gate driver with organic thin-film transistors (OTFTs). The dual-gate OTFT devices have a field effect mobility of 0.78 cm2/Vs, and on/off current ratio above 108. A single stage of the gate driver consists of ten TFTs and two capacitors, with small pitch of 244 μm. The fabricated circuit has a minimum pulse width of 5μs, which is compatible with full-high definition (FHD, 1920 × 1080) active-matrix displays with 60Hz frame rate. It can work at input swing of as low as 10V, with VGH2, VGH1, and VGL of 5V, 0V, and −10V respectively. With the threshold voltage shift under positive and negative bias stress, the gate driver shows output signals without significant degradation and demonstrates its high reliability through simulation.

Reliable Gate Driving of SiC MOSFETs With Crosstalk Voltage Elimination and Two-Step Short-Circuit Protection

The over-stress of the negative gate-source voltage of SiC MOSFET, even in a short period of time, could cause the threshold voltage drift of the device, resulting in increased on-state resistance. In this paper, we propose an integrated gate driver to specially limit the peak negative gate voltage of SiC MOSFETs introduced by the crosstalk phenomenon and the reliable short-circuit protection. A simple auxiliary branch with bidirectional blocking capability is adopted in crosstalk voltage suppression and the negative peak voltage of the gate, introduced by common source inductor, is eliminated by the high impedance gate driving loop. Furthermore, the auxiliary circuit is re-used to assist a two-step short-circuit protection of the device by identifying dc-link shoot-through current on the stray inductor. By rapidly reducing the gate-source voltage to a lower value when short-circuit happens, the short circuit withstanding time of the device is prolonged, enabling a longer allowable detection time to confirm the fault event accurately. The proposed method comprehensively integrates the crosstalk voltage suppression and short circuit protection together and is verified by the experiments.

Switching of GaN CAVET With Quasi-Monolithic Integrated HEMT Gate Driver

Switching of GaN CAVET With Quasi-Monolithic Integrated HEMT Gate Driver

24‐2: Facile Design of Integrated Gate Driver Circuit with Self‐aligned InGaZnO TFTs and Reliable Compensation Technology for 166 PPI WOLED Displays

In this research, we describe a facile design of white organic light emitting diode (WOLED) displays applicable to 8K4K resolution of large‐area displays. We demonstrated a 13.3‐inch diagonal size (166 pixel‐per‐inch) of WOLED display, including a self‐aligned oxide thin‐film transistors, simple pixel driving circuit, external compensation method, fast driving integrated gate driver circuit. The narrow bezel of 3.9 mm is realized when multi‐output gate driver circuit is applied. The required function for external compensation method is realized by the integrated gate driver circuit. The external compensation improved global luminance uniformity, especially at the low gray level.

A novel ultra large size organic light emitting diode display for premium televisions

AbstractIn this paper, we present novel ultra large size organic light emitting diode (OLED) display technologies with high image quality for premium televisions (TVs) using an advanced coplanar oxide thin film transistor (TFT) backplane, microlens array (MLA)‐based OLED, small size gate driver in panel for narrow bezel, and pixel charging enhancement method with external compensation. Using these technologies, we improved the luminance efficiency about 20% and reduced the integrated gate driver design area to 40%. We have achieved the life time of the gate driver in panel longer than 100,000 h in reliability test. The pixel charging ratio is more than 80% in all gray levels. Using the developed OLED display, we have successfully developed up to ultra large size 88‐in. 8K and 97‐in. 4K OLED TVs.

P‐1.10: Robust Amorphous IGZO Integrated Gate Driver Circuit for Ultra Large TFT‐LCD Applications

Recently, a‐IGZO TFTs have attracted considerable attention for ultra large‐sized and ultra high‐resolution display due to high mobility and good uniformity. The life‐time of integrated gate driver is mainly determined by the stability of low‐level maintaining and pull‐up TFTs, which always experience severe performance degradation after a long time operation. In this paper, a robust a‐IGZO integrated gate driver with dual lowlevel maintaining units is proposed and fabricated for ultra large‐sized and high resolution TFT‐LCD applications. The simulation and BTS measurement results demonstrate that proposed a‐IGZO gate driver has a large VTH shift margin, which contributes to extended life‐time of circuit operation.

An Integrated Gate Driver Based on SiC MOSFETs Adaptive Multi-Level Control Technique

In HV (high-voltage) and HF (high-frequency) applications, SiC (silicon carbide) MOSFET is widely used for its small parasitic characteristics and fast switching speed. Using discrete devices on PCB, the active gate driver is usually adopted to restrict EMI (electromagnetic interference) noise. This method could achieve a limited switching performance improvement, and many disadvantages still exist. In this paper, the integrated adaptive multi-level gate driver is presented to improve the switching performance of SiC MOSFET in HV and HF applications. The proposed gate driver is realized on the chip using critical techniques such as <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dV/dt</i> noise attenuation, high-speed circuit, and anti-false triggering mechanism. Then, the proposed gate drive is fabricated in a 0.18 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> m BCD process and occupies a 4.16 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> active area. The experimental results show that SiC MOSFET can achieve a 200 ns switching time, 0.8 mJ energy losses, no more than 15 V/ns average <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dV/dt</i> noises, and 1.5 A/ns average <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">di/dt</i> noises under a 600 V power supply and a 33 A load. SiC MOSFET can also realize the excellent switching performance at different load currents from 15 A to 90 A by using the proposed adaptive multi-level gate driver.

Characterization of GaN HEMTs' Aging Precursors and Activation Energy Under a Wide Range of Thermal Cycling Tests

In this paper, 650 V / 7.5 A rated enhancement-mode (E-mode) Gallium Nitride (GaN) high-electron-mobility-transistors (HEMTs) with integrated gate drivers are characterized under thousands of accelerated thermal cycles (ATC) at different junction temperature stresses. This research helps in developing fundamental insights into GaN HEMTs' aging characteristics through the degradation of ten devices under ATC tests. For over 20,000 thermal cycles, the forward and reverse conduction losses, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> GSS, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> oss, and the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RDS</i> on are experimentally measured to identify the parameter shifts and the corresponding precursors. Results indicate that both <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IGSS</i> and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> oss do not deviate much, but the values of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RDS</i> on, the forward and reverse conduction losses vary considerably with device aging. This paper also presents an empirical method to estimate the correlation between the acceleration factors of the GaN FETs' degradation process and the thermal cycling conditions. The value of the activation energy of the tested GaN HEMT devices is also derived using the empirical equations to be about 1.13 eV under the applied stress factors. This study finds that the degradation process of GaN HEMTs with age facilitates a reasonable correlation with different failure mechanisms, which further helps in reliability improvement.

High-reliable Integrated Gate Driver GOA TFT development under Extremely High Intensity Illumination for Large-Size UHD LCDs Outdoor display applications

The 29th International Display Workshops (IDW '22),High-reliable Integrated Gate Driver GOA TFT development under Extremely High Intensity Illumination for Large-Size UHD LCDs Outdoor display applications

A PCB-Embedded 1.2 kV SiC MOSFET Half-Bridge Package for a 22 kW AC–DC Converter

This article presents the design and analysis of a double-side-cooled printed circuit board (PCB) embedded silicon carbide (SiC) MOSFET half-bridge package with low loop inductances and an integrated gate driver. The 1.2 kV SiC MOSFET dies used in the half-bridge package are embedded in the PCB using AT&S's patented technique. The dies are cooled and electrically connected to traces in the PCB through copper-filled microvias. The design methodology accounts for both electrical and thermal performance, limiting the power-loop inductance to 2.3 nH and the maximum package temperature to less than the 175 °C limit. The integration of the gate drive circuitry allows for a high power density and 2.2 nH gate-loop inductances. At 0.12 K/W, the measured junction-to-case thermal resistance with double-sided cooling is 57% lower than that of a TO-247 package. Under similar operating conditions, the PCB-embedded half-bridge package also achieves a 5.6 times lower voltage overshoot and a 0.5% higher peak efficiency than a TO-247-based half-bridge. This article reports the first demonstration of PCB-embedded 1.2 kV SiC MOSFET packages in buck, boost, and ac–dc converters. The prototype three-phase ac–dc converter for an electric vehicle on-board charger is composed of six PCB-embedded half-bridge packages and achieves an efficiency of 98.2% and a power density of 182 W/in <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> .

An Integrated Driver With Bang-Bang Dead-Time Control and Charge Sharing Bootstrap Circuit for GaN Synchronous Buck Converter

This article proposes a high-frequency integrated gate driver for gallium nitride (GaN) synchronous buck converter. The proposed adaptive bang-bang dead-time control minimizes dead-time at any load condition. Thus, it mitigates the excessive power loss caused by GaN device reverse conduction in high-frequency applications. The proposed charge sharing bootstrap circuit ensures sufficient gate overdrive voltage with reduced chip area. Fabricated in a TSMC 0.25- <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> m BCD process, the driver integrated circuit enabled GaN-based buck converter to operate at 10 MHz switching frequency with minimal dead-time to as low as 0.4 ns under light load and heavy load conditions. Compared with fixed dead-time control, the proposed work improves around 5% efficiency under heavy load condition. The fully integrated bootstrap circuit with 100 and 60 pF (HV) capacitor obtained the lower than 0.6 V driving voltage drop with only 45% capacitance and around half of the voltage drop compared with a conventional bootstrap circuit. Besides, the proposed driver successfully tackled the parasitic ringing and dead-time overcharging issues in the GaN converter.

P‐10: Emit Signals Reused Gate Driver Design for Ultra‐Narrow‐Bezel Micro‐LED Display Based on Metal‐Oxide TFTs

A compact integrated gate driver using metal‐oxide TFTs is proposed for Micro‐LED display. The positive pulse generation module (i.e. Scan driver) and negative modules (i.e. Emit driver) are located at different side of the Micro‐LED display, respectively. While Emit signals are re‐used for low‐level‐maintaining of the Scan module, the gate driver design can be much simplified and area occupation of the single gate driver can be reduced to 90 μm(length)× 245 μm(height), while the length of conventional designs exceeds 1000 μm. The simulation results of cascaded gate driver show that the rising time and falling time of the circuit are reduced to 1.3 μs and 2.1 μs, respectively, with the gate loading of 1.5 kΩ and 150 pF.

A-Si TFT Integrated Gate Driver Workable at −40°C Using Bootstrapped Carry Signal

A thin-film transistors (TFTs) integrated gate driver which can work well at low temperature down to -40 °C is proposed and demonstrated. The carry signal (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</sub> ) of the driver, being generated through the voltage bootstrapping approach using a C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</sub> -connected capacitor, is used to pre-charge the following stage of the driver. As the rising and falling time of C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</sub> is much shorter than that of the gate driving signal G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</sub> , the bootstrapping voltage is increased and voltage loss of the pre-charge transistor can be much reduced, to avoid the driver’s malfunction at low temperature. This structure further benefits maintaining the driving speed over long operation time at high temperature. On the other hand, the G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</sub> , instead of C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</sub> , is used to reset the gate driver to suppress the voltage feed-through effects. One single stage of the driver consists of 11 TFTs and 2 capacitors, driven by 4 clock signals with the duty ratio of 25%. An a-Si:H TFTs implemented single stage circuit of the driver occupies an area of 250 μm×1099 μm. Measurements show that the output voltage magnitude can be maintained well when temperature varies from -40 °C to 80 °C. Moreover, the rising-time and falling-time increase of the output pulse are both less than 3 μs after 240 hours of the accelerated high temperature aging operations.

Development of a current source resonant inverter for high current MHz induction heating

High frequency industrial induction heating processes typically employ resonant inverters to reach high efficiency at high power levels. Advancements in wide band gap (WBG) device technology has made it feasible to push the possible frequency of these processes into the MHz regime using solid state technology. Several topologies can be applied, each with advantages and drawbacks. This paper presents a current source resonant inverter (CSRI) employing a custom designed power module utilizing 1700V SiC MOSFETs for MHz operation of a high-Q resonant tank for induction heating, which presents new challenges in the inverter module design. An integrated gate driver structure is demonstrated driving four MOSFETs in parallel in MHz operation. Theoretical analysis predicts substantial parasitic influence on inverter operation, and thus an inverter is constructed to provide experimental verification of MHz operation, while the challenges associated with high frequency CSRI operation are discussed. In the experimental inverter setup, the fabricated power module achieves > 90 % efficiency for a calculated reactive power of 170 kVA and 2.3 kW output power during unloaded operation, validating the inverter design for extension to higher power loaded operation.

2.1: Invited Paper: 16.9‐Inch Flexible AMOLED Display with High Performance Top Gate Oxide TFT

We have fabricated top‐gate IGZO TFTs on PI substrate, which exhibit excellent electrical properties and high mechanical reliabilities to meet the demand for large area flexible display. The ΔVth under PBTS and NBTIS for 10 hours are only +0.26 V and −0.34 V, respectively. The mechanical bending properties of the TFT backplane is investigated. There are almost no change after 200,000 bending cycle test at a curvature radius of 20mm. To improve flexible capability and reduce cost of flexible OLED display, integrated gate driver on array (GOA) circuits with spilt channel structure has been investigated. Finally, we successfully realize 16.9‐inch rollable OLED display with high performance top gate IGZO TFT and GOA circuits

34.3: High Reliable Integrated Gate Driver GOA Circuit using Four‐Mask a‐Si TFT for Large Size UHD LCD TVs

Gate driving circuit (GOA) design is critical to reduce the production cost and narrow border TFT‐LCD. The proposed GOA circuit has the optimized TFT W/L design and TFT stress reduction which enhances gate driver reliability for TV application. We developed 50UHD 120Hz TFT‐LCD with GOA circuit using 4‐mask a‐Si TFT.

2.4: Integrated Gate Driver Circuit Technology with IGZO TFT for AMOLED Displays of Simultaneous Emission Driving Method

In this paper, we propose a new integrated gate driver circuit for a simultaneous emission (SE) driving method using IGZO TFT. Simulation results indicate that the proposed gate driver prevents the output waveforms the effect of positive and negative biases, and VTH variations of IGZO TFTs. Furthermore, the proposed circuit is suitable for AMOLED displays with the SE driving method.