Integrated Circuit Packaging Research Articles

Upgrading Die Attach Machine Capability for Micro Electromechanical Systems Package

The paper discussed the study and challenges of the Die Attach process, the critical characteristics of the product structure and the demand for the MEMS product. Upgrading the current machine mechanical and software to improve the machine's capabilities and overcome the criticality of the product structure, such as; 30 microns Die Placement accuracy, can process Wafer with dual Die Orientation 0 and 180 degrees, capable of detecting incorrect die orientation and finally can process thin substrate with 130 microns thickness. After machine upgrades, statistical validation using Two Proportion tests was used to help validate the machine's performance efficiently. The new upgraded machine has the same capability and performance as the new die attach machine model, therefore the upgrade and enhancement on the old model Die Attach machine are effective and efficient.

Sintered Nanocopper Paste for High-Performance 3D Heterogeneous Package Integration

Fifth-generation (5G) communications have been driving major package innovations to enable low-loss interconnects between the integrated circuits (IC) and other system components such as antenna arrays. Antenna-in-package with three-dimensional (3D) or double-side component is widely pursued as the front-up architecture to realize this vision. The interconnect height and losses are critical parameters in these 3D package structures. Copper sintering paste is emerging as an ideal candidate to replace solders for both off-chip and on-package interconnects because of the resulting higher electrical conductivity and relatively simple manufacturability with additive processes. This article focuses on computational modeling, optimization of sintering conditions, and electrical conductivity measurements of highly conductive copper paste to verify the proposed model. The model is based on two-particle sintering theory, which describes the neck growth evolution of copper paste at the initial stage of sintering. The neck-growth model shows good consistency with the measured neck size of copper, and hence can be used to provide guidelines for the sintering conditions of copper paste. The celectrical conductivity measurements suggest that the copper paste sintered at 260°C for 30 min shows a electrical conductivity of 1.4 × 107 S/m, which is 82% higher than that of solder. In addition, this article investigates the potential of copper paste interconnect technology in high-frequency applications such as in 5G millimeter-wave communications. The transmission lines patterned with the copper paste show good correlation with simulated results in the millimeter-wave frequency band. The high-frequency characterization also indicates that the copper paste enables simple circuit patterning, offering equivalent signal losses with plated copper. The detailed analyses discussed in this article suggest the eligibility for multi-applications of copper sintering paste in IC packaging.

Ultra-low Residue Flux Applications in RF Front-End Packages

Abstract With the leap into the 5G era, the demand for improvements in the performance of mobile phones is on the rise. This is also true for the quantity of radio frequency (RF) front-end integrated circuits (ICs), especially for RF switches and low noise amplifiers (LNA). It is well-known that improvements in performance depend on the combination of new design, package technology, and choice of materials. Ultra-low residue (ULR) flux is an innovative, truly no-clean, flip-chip bonding material. By using ULR flux, the typical water-wash cleaning process can be removed and, in some instances, package reliability can be improved as well. This simplified assembly process will help to reduce total packaging costs. This paper will discuss the application of ULR fluxes on land grid arrays (LGAs) and quad-flat no-leads/dual-flat no-leads (QFN/DFN) packages for RF front-end ICs, as well as the reflow process. The solder joint strength and reliability study will be shared as well.

Package Substrate Die Pad Roughening Innovative Solution to Strengthened Die Attach Adhesion

Poor die adhesion to substrate resulting to stray dice issue for the MEMS package was encountered. This die bond failure mechanism has a downstream effect specifically on the mold process. The presence of the stray die resulted to mold compound leakage outside the tool cavity due to planarity not achieved. The mold compound that leaks affected the overall package thickness, thus exposing the wires.
 Using the Design of Experiment methodology, the team generated different simulations and validations to resolve the stray die problem. Based on the simulation and experiments, it was established that an optimum substrate roughness is necessary to achieve a better adhesion between the Die adhesive and the substrate. 
 This paper presents a systematic study on how the substrate roughness can improve the adhesion of Die Attach film (DAF) to the substrate thereby resolving the Stray Die problem. Results showed that the die adhesion strength on the substrate increases as the substrate surface roughness increased from Ra 0.05 um to Ra 1.5 ~ 2.0 mm. Consequently, the rejection rate of stray dice was eliminated. This new learning will be used to establish a standard on surface roughness for substrate-based material that can be applied to new packages.

Effect of Epoxy Molding Compound Material and Roughness Leadframe to Integrated Circuit Package for Automotive Devices

This research studied about an effect of epoxy molding compound material and roughness leadframe of integrated circuit package for automotive device. In manufacturing process, the epoxy molding compound material and leadframe roughness are main factors that effect to coefficient of thermal expansion (CTE) and reliability for automotive device package with no delamination in high temperature application. In experiment, two types of epoxy molding compound materials were studied and compared between standard and roughened leadframe for quad flat non lead (QFN) package. For reliability test, the epoxy molding compound materials type A and type B with different leadframe were analyzed with moisture sensitivity level 1 to observe delamination inside packages. The results showed that CTE of epoxy molding compound material type A is less CTE mismatch than that of epoxy molding compound material type B with both standard and roughness leadframe. Moreover, the results also found no delamination for epoxy molding compound material type A with roughened leadframe. In addition, both epoxy molding compound materials showed significant delamination inside packages with standard leadframe.

Die Attach Pre-bond Inspection Innovation for Roughened Leadframe

This paper studies the challenges and behavior of epoxy material between the roughened Leadframe during the Die Attach process. Die bond on the roughened die-attach paddle (DAP) of epoxy has been a challenge for its manufacturability in terms of maintaining the target epoxy volume. The study on the roughened Leadframe utilizing the Pre-bond inspection parameter causing machine inspection cannot fully detect the epoxy pattern. The uneven contrast of pad’s, causing pre-bond inspection problem. Hard to teach / set-up epoxy inspection due to the contrast between leadframe die pad vs. epoxy. The roughened leadframe property has different surface contrast causing Frequent “Bond Align” and epoxy inspection error on the Roughen leadframe. This occurrence leads to risks of insufficient epoxy which is detrimental to product reliability (delamination on die bottom) and can cause manufacturing yield loss due to insufficient epoxy coverage. Using the Design of Experiment (DOE) methodology and its applicable statistical tools, the author to come up with error-proofing solutions to resolve and reduce the Insufficient Epoxy. The innovative and breakthrough solutions implemented were the installation of ultra-bright light with double sidelights in pre-bond inspection which is the key in reducing defects rate.

Estimation of Silicon Wafer Coating Thickness Using Ultrasound Generated by Femtosecond Laser

Abstract As one of the fastest-growing technologies over the past half century, integrated circuit (IC) packaging is getting smaller and more complex. For example, typical silicon wafers in modern IC packaging have thicknesses ranging from several to tens of micrometers, and their coating layers are in the range of a few nanometers. Because the silicon wafer is the main substrate in IC packaging, it is important to accurately measure the geometry of a silicon wafer, especially its coating thickness, for process monitoring and quality control. In this study, an ultrafast ultrasonic measurement system is developed using a femtosecond laser for silicon wafer coating thickness estimation. The proposed technique provides the following unique features: (1) an ultrafast ultrasonic measurement system using a femtosecond laser is developed specifically for silicon wafer coating thickness estimation; (2) the developed system can estimate the thickness of a coating layer in the range of sub-micrometer; (3) except for the wave speed in the coating material, coating thickness can be estimated without any other prior knowledge of the coating material properties or substrate characteristics such as optical constants; and (4) the thermal effects on the ultrasonic waves propagating within a thin coating layer are explicitly considered and minimized for coating thickness estimation. Using the developed system, validation tests were successfully performed on gold-coated silicon wafers with different coating thicknesses.

Characterization of On-Foil Sensors and Ultra-Thin Chips for HySiF Integration

The characterization of multiple mechanically flexible passive and active electronic components, namely on-foil temperature sensor, relative humidity sensor, and ultra-thin microcontroller unit (MCU) integrated circuit (IC) is presented. These components are readily available for Hybrid System-in-Foil (HySiF) integration, which combines the merits of the high-performance silicon chips with the large-area electronics. The 60-nm thin-film resistance temperature detector (RTD) is fabricated on different substrates and the extracted temperature coefficient ranges from 0.002 to 0.003( $\Omega/\Omega$ )/°C. Furthermore, the capacitive relative humidity sensor is fabricated by utilizing a polymeric sensing dielectric material that is compatible with those polyimides used in ultra-thin chip embedding. The $1-\mu \text {m}$ thick sensor achieves a fast adsorption rise time of $\text {54 ms}$ and a spontaneous desorption fall time of $\text {750 ms}$ . For flexible ICs packaging and HySiF integration, microcontroller chips are back-thinned to a thickness of about ${30}~\mu \text {m}$ . The characterization of the MCU after the thinning process step showed undegraded performance of the integrated analog-to-digital converter in terms of linearity. However, a drop in the on-chip temperature sensor sensitivity is observed for the thin chips and significant degradation in the period jitter of the high-frequency RC oscillator is measured. Finally, continuity tests are performed to validate the functionality of the ultra-thin MCUs when embedded using the Chip-Film Patch (CFP) flexible package.

Die Attach Process Optimization with Enhanced Epoxy Control on Leadframe Package

The paper presents a practical procedure in selecting the best candidate for die attach epoxy control or anti-epoxy bleed-out (anti-EBO) concentration during the introduction of new leadframe configuration. Three different criteria were implemented to measure the relative impact of the anti-EBO into the different interfaces inside a quad-flat no-leads multi-row (QFN-mr) leadframe unit. Die shear test is performed to measure the shear strength and the compatibility of the anti-EBO to the adhesive material. EBO measurement is performed herewith to study the propagation of epoxy bleed-out on the surface of the leadframe with reference to the different level of anti-EBO concentration. Package reliability is employed study the response of different interfaces directly in-contact with anti-EBO through thermal-cycling scenario. Ultimately, understanding the effect of anti-EBO into different set of tests provided a systematic way of selecting appropriate leadframe parameters for QFN-mr leadframe product.

Development of High Thermally Conductive Die Attach for TIM Applications

Abstract High-power semiconductor applications require a thermal interface die attach material with high thermal conductivity to efficiently release the heat generated from these devices. Current thermal interface material solutions such as thermal grease, thermal pads, and silicones have been industry standards, however may fall short in performance for high-temperature or high-power applications. This article focuses on development of a cutting-edge die attach solution for thermal interface management, focusing on fusion-type epoxy-based Ag adhesive with an extremely low storage modulus and the thermal conductivity reaching up to 30 W/mK, and also very low-modulus, low-temperature pressureless sintering silver die attach with a thermal conductivity of 70 W/mK.

Detection of Sealant Delamination in Integrated Circuit Package Using Nondestructive Evaluation

Abstract This paper presents the development of a nondestructive evaluation method for delamination detection in integrated circuit (IC) packages. The developed method allows for quantitative detection of sealant delamination between integrated heat sink (IHS) and substrate, which is considered a potential failure mechanism in IC packages. The proposed method is expected to overcome the destructive nature of most existing techniques, while maintaining low cost of development. The reported development consists of the following processes: First, flash thermographic analysis is investigated and shown to be incapable of detecting a realistic sealant delamination. Then, ultrasonic guided waves (UGWs) are used as the chosen interrogation method due to their sensitivity to small-size damage and structural thickness variations. The complexity of the received ultrasonic signals caused by the geometric heterogeneity is resolved using a time–frequency signal processing technique. The extracted ultrasonic information, including time-of-arrival (TOA) and amplitude of wave modes received from different sensing paths under multiple excitation frequencies, is then used to construct a feature space. A multivariate Gaussian model is implemented as an information fusion and delamination detection tool, which investigates the distribution of feature space including correlations between features. Results from the developed model are compared with two existing evaluation methods, including pullout force measurement and a delamination metric. The developed method is seen to possess a similar level of accuracy with a nondestructive nature.

A Study of Micro-crack on Surface Mount IC Package

In integrated circuit (IC) manufacturing industry, package micro-crack and other crack-related flaws are common defect frequently encountered in trim and form process of a surface mount IC package. This paper focused on the prevention of the micro-crack occurrence as it affected the assembly yield performance of the device in focus. Process mapping and defect concentration diagram were done to isolate the location of the defect and the processes involved. Containment and corrective actions were employed to fully narrow down the defect occurrence. Finally, a 99% improvement on defect parts per million (ppm) reduction was observed after implementation of all corrective actions.

The two-phase flow simulation and experimental research on the formation of solder voids in power module

This paper focuses on the formation of solder voids in the large-area die-attach (DA) in power modules. The finite volume simulation method was used to study the motion behaviors of bubbles in molten liquid solder. The experiments were carried out by changing the reflow atmosphere. The voids distribution in DA was characterized by X-Ray detection. Results suggest that vacuuming the molten solder can significantly reduce the void rate of the DA. The bubbles only need a short stroke to escape from the molten solder under the influence of negative pressure. From a mechanical point of view, the collapse of the solder during the phase change is one of the main forces for driving the bubble to coalesce and move horizontally, but it may also lead to an increase in void ratio due to the reduction of BLT (Bond Layer Thickness). Solders with larger wall contact angles tend to have a larger void rate due to the increase in viscous resistance. The nitrogen atmosphere has a positive effect on reducing the void rate by reducing the wall contact angle of liquid solder. Besides, the wall adhesion plays a leading role in the movement of the bubble, and the influence of the buoyancy is small.

Die Attachment Method on a Cu Finish by Pressure-Assisted Sinter Bonding in Air Using Cu Formate Paste

Die Attachment Method on a Cu Finish by Pressure-Assisted Sinter Bonding in Air Using Cu Formate Paste

A Study of Integrated Circuit Dicing Tape When Used in a Plasma Dicing Environment

The main objective of this article is to establish which of the many dicing tapes used in the semiconductor industry would be most suitable for use in plasma dicing. Tape design over the past 40 years has continually evolved through advancements in both dicing technologies and the incessant revision of integrated circuit packaging. Die singulation has traditionally been accomplished using a diamond saw, laser-based technology, or a combination of both. The stress on dicing tape was, therefore, limited to fatigue through the physical nature of saw dicing or heat energies induced during laser dicing. These processes do not expose dicing tape to either a high vacuum or a variety of plasma chemistries. This investigative work is a continuation of studies examining the dicing tape behavior when used in plasma dicing. Results show that polyolefin (PO) UV tape with low-to-medium adhesion strength exhibits the greatest resilience under harsh plasma etch conditions and that efficient photoinitiated cross linking (or curing) of the adhesive is triggered if directly exposed to the photonic energies present in a pure SF6 plasma or full plasma dicing process. However, the postplasma dice, post-UV cure adhesive strength can still be minimized if the tape manufacturers recommended time limitations between which the tape mount, plasma dice, and die pickup process are adhered to.

Microstructural evolution and shear performance of AuSn20 solder joint under gamma-ray irradiation and thermal cycling

Owing to the excellent stability and mechanical strength, AuSn20 solder is of particular importance to the die attachment in aerospace power modules. An elevated requirement was put forward to improve the performance of solder joints for next-generation aerospace electronics. To this context, the microstructural evolution and mechanical performance of AuSn20 solder joints under independent γ-ray irradiation and thermal cycling were investigated in this work. The experimental results reveals that the shear forces of AuSn20 micro-joints were reduced by 17.5% and 25.3% after 1000 h of γ-ray irradiation and 200 thermal cycles, respectively, which are caused by the increase of interfacial IMC (intermetallic compound) layers and voids. Generally, the experimental data presented here are highly prospective because it provides new insights for the solder joint reliability in space environment, which could advance the research progress of aerospace devices without RHBD (radiation hardening by design) and ATCS (active thermal control system).

Improvement of Productivity through the Reduction of Unexpected Equipment Faults in Die Attach Equipment

As one of the semiconductor back-end processes, die attach process is the process that attaches an individual non-defective die (or chip) produced from the semiconductor front-end production to the lead frame on a strip. With most other processes of semiconductor manufacturing, it is very important to improve productivity by lessening the occurrence of defective products generally represented as losses, and then find the fault causes which lower productivity of the die attach process. Thus, as the case study to analyze quantitatively the faults of the die attach process equipment, in this research, we developed analysis systems including statistical analysis functions to improve the productivity of die attach process. This research shows that the developed system can find the causes of equipment faults in die attach process equipment and help improve the productivity of the die attach process by controlling the critical parameters which cause unexpected equipment faults and losses.

Critical Insights in the Application of Convection and Pressure Curing in Eliminating DAF Voids

The absent of reliable production controls for Die Attach Film (DAF) voids detection allowed defect escapee for Ball Grid Array (BGA) devices using non-conductive film material leading to gross assembly rejection and customer complaints. This paper presents the evaluation of pressure curing as an alternative to the convection curing in die attach process with additional capability to eliminate the DAF voids on non-conductive films. Through Analysis of Variance (ANOVA) analysis, green peeling test, Scanning Acoustic Microscope (SAM), cross section analysis and reliability test performed between samples arrives to the conclusion that pressure oven has a significant impact in die shear strength improvement and DAF voids elimination with positive response in reliability requirement. The result of the study improves the assembly flow and production control of BGA devices through the transition of convection to pressure curing technology.

Design of Signal Generators Using Active Elements Developed in I3T25 CMOS Technology Single IC Package for Illuminance to Frequency Conversion.

This paper presents a compact and simple design of adjustable triangular and square wave functional generators employing fundamental cells fabricated on a single integrated circuit (IC) package. Two solutions have electronically tunable repeating frequency. The linear adjustability of repeating frequency was verified in the range between 17 and 264 kHz. The main benefits of the proposed generator are the follows: A simple adjustment of the repeating frequency by DC bias current, Schmitt trigger (threshold voltages) setting by DC driving voltage, and output levels in hundreds of mV when the complementary metal-oxide semiconductor (CMOS) process with limited supply voltage levels is used. These generators are suitable to provide a simple conversion of illuminance to frequency of oscillation that can be employed for illuminance measurement and sensing in the agriculture applications. Experimental measurements proved that the proposed concept is usable for sensing of illuminance in the range from 1 up to 500 lx. The change of illuminance within this range causes driving of bias current between 21 and 52 μA that adjusts repeating frequency between 70 and 154 kHz with an error up to 10% between the expected and real cases.

Efficient Approach for Electrical Design and Analysis of High-Speed Interconnect in Integrated Circuit Packages

In recent integrated circuit (IC) packages, the structure of the interconnect is highly complex, and the effect of high-frequency parasitics is significant. These factors increase the number and level of design variables and extend the analysis frequency range to tens of gigahertz. As a result of the high dimensions of the design space, it is difficult to reduce the design gap between the current design approach and the physical limits of the practical IC-package interconnect. In this paper, we present an efficient approach for designing and analyzing the electrical characteristics of the high-speed interconnect in IC packages. The proposed approach is developed using a hybrid method involving the design of experiments, the domain decomposition method, and the finite-element method. We present a procedure to identify critical design variables for the IC-package interconnect, and we derive a method to recombine the impedance parameters of a segmented interconnect. The proposed hybrid method is verified by comparing its characteristic impedance (Zo) with the Zo value from a full-wave simulation of a complete interconnect. We demonstrate that the proposed hybrid method significantly reduces the design space of the IC-package interconnect so that we can efficiently and rapidly obtain the optimized solution, thereby improving the system performance.