Integrated Circuit Design Process Research Articles

A fine-grained detection method for gate-level hardware Trojan based on bidirectional Graph Neural Networks

Due to technical barriers and economic costs, malicious circuits, known as hardware Trojans, are easily implanted in the complicated integrated circuit design and manufacturing process, which can lead to many disastrous consequences, such as denial of service, information leakage, performance degradation, etc. Research on how to detecting hardware Trojans has grown into a significantly open issue over the past decade. While, for very large scale integrated circuits, numerous new challenges deserve our full attention, including golden-free chip reference, automatic feature engineering, hardware Trojan localization, and scalable framework. In response to the above challenges, a fine-grained gate-level hardware Trojan detection approach is proposed in this paper, named GateDet, from improving earlier circuit graph modeling to developing a detection framework based on Bidirectional Graph Convolution Networks with a timely information fusion strategy. GateDet achieves automatic feature circuit extraction and further overcomes the original neighborhood limitation of Bidirectional Graph Convolution Network. Moreover, for large-scale training, it comprehensively considers the problems of sample imbalance and boundary network, and develops a circuit directed graph sampling method based on GraphSAINT, which improves the training performance of the directed graph framework. From experiments, GateDet shows high scalability on 24 benchmarks of TrustHub. It could be used to learn about adaptive structural feature extraction for different Trojans simultaneously. Compared to the existing gate-level detections, the fine-grained results of GateDet are more accurate and can be used to track suspicious structures, reducing manual review.

Recurrent neural network implementation of digital integrated circuits to mitigate challenges in design verification

Design verification is the dominant stage that consumes the most resources in the digital integrated circuit (IC) design process. Design verification is important because human designers imperfectly convert high-level specifications to low-level circuit implementations using standard cell logic, which is nonlinear and complex to predict and characterize. The widening process variations in shrinking process technologies while digital designs grow in scale and complexity to the extent of being impossible to fully or intuitively identify all temporal interactions of a specific design. Deep neural networks (DNN) are being progressively integrated into the sophisticated software tool chain and design process flow of digital IC as artificial intelligence can learn relationships and correlations in complex, high-dimensional, and multi-factorial problems. In this work, we propose to apply DNN to implement digital IC to minimize the complexity of digital design verification. We posit that DNN can learn to implement circuit functions directly from high-level specifications without requiring detailed specifications from the designer. Trained neural networks can be implemented on neuromorphic hardware to achieve greater power and compute efficiencies than the conventional standard cell implementation. We demonstrate that over 150 randomly generated finite state machines (FSM) can be learned effectively with Recurrent Neural Network (RNN) comprising Gated Recurrent Units (GRU) with different complexity as indicated by the number of states and inputs to the FSM. Our proposed methodology of learning RNN GRU implementations of FSM demonstrates a way forward to reduce the cost and effort of design verification, ultimately leading towards faster digital IC design cycles.

Optimization And Analysis of Furnace Temperature Profile for The Processing Technology of Electronic Components

The soldering furnace is an important piece of equipment for processing and soldering electronic components in the integrated circuit design process. After the printed circuit boards are mounted with various electronic components, they are placed in the soldering furnace for heating so that the electronic components are automatically soldered to the circuit boards. In this process, the furnace temperature profile, which records temperature data of the electronic components, is an important reference indicator for measuring the effectiveness of electronic component processing. In the context of electronic component soldering, the transfer speed of the furnace and the setting of the temperature in each temperature zone are decisive in ensuring the quality of the component soldering. Based on the Newton's law of cooling and heat equation, this paper establishes several mathematical models to study the effect of the temperature setting of each temperature zone and the transfer speed of the soldering furnace on the furnace temperature profile with the help of multi-objective planning, circular search algorithm and other mathematical methods. Finally, the corresponding conclusions and optimization methods of furnace temperature profile are drawn, which have certain significance for the processing of electronic components.

Design architecture and algorithm of wireless network integrated circuit based on 5G+AI

In the current integrated circuit (IC) design process, research on its design process is relatively backward. This paper mainly adopts 5G + artificial intelligence technology, and conducts an in-depth discussion on the structure and algorithm of wireless network integrated circuits. The article analyzes the development of IC industry and the application of EDA software, and puts forward some problems that China’s IC industry is currently facing. The article discusses the realization of IC design flow, which is realized from five aspects: design input, function simulation, layout realization, physical verification, and post-parasitic simulation. Then, in view of the problems existing in the current IC design process, specific solutions for improvement and strengthening are given. Four parts are designed in detail, namely multi-mode simulation, realization of fully automated layout, feature extraction and modeling, IR Drop and EM analysis. Combined with the widely used characteristics of IP design reuse technology, this paper conducts a targeted research on the process of IP design reuse. From the IP circuit transplantation and IP layout transplantation, the specific discussion is carried out. From the perspective of IP design reuse, the design process of the wireless network integrated circuit is further improved. This paper turns to the design of RF IC from the perspective of IC design process, giving the flow chart of RF chip. The test results showed that over the full temperature range, the total current was about 2.45 mA, which met the design requirements. When the load resistance is 4KΩ, the ascending propagation delay is 92tns and the descending propagation delay is 65tns, both of which increase significantly. The article can provide further reference for the design of wireless network integrated circuits.

ACED-IT: Assuring Confidential Electronic Design Against Insider Threats in a Zero-Trust Environment

The electronics supply chain has adapted into a global process over the past two decades to support the cost of process optimization. As the semiconductor industry has transitioned from a vertical to the horizontal business model, the perceived vulnerability of integrated circuit (IC) design, and fabrication has grown dramatically. Design intellectual property (IP) is the defining characteristic of most fabless design houses and integrated device manufacturers (IDMs) within the supply chain, and as such, holds significant value for market competitiveness, and in some cases, national security. Malicious insiders threaten the confidentiality of this proprietary technology. To prevent IP piracy, we redefine the modern threat landscape by considering nearly every individual in the IC design and fabrication process untrusted. Therefore, we propose a novel framework to assure confidential electronic design against insider threats, termed ACED-IT, that enables maintaining the confidentiality of the design when it traverses through different design stages (e.g., RTL/Gate-level to GDSII). ACED-IT integrates encryption, logic locking, novel temporary-inserted logic elements (TILEs), access controls, and action logging, to protect the design IP from insider threats originating from any entity in the process. ACED-IT is compatible with the current industry development flow and provides all engineers with the tools to complete their roles. The proposed ACED-IT framework is demonstrated across various benchmarks and analyzed for security. Benchmarks processed using ACED-IT incurred negligible overhead across parameters such as power, area, timing, and test coverage after functional recovery, and provided a brute force attack complexity to recover the original design exceeding that of AES-256.

Design for High Reliability of CMOS IC With Tolerance on Total Ionizing Dose Effect

As the standard complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) generates a leakage current due to ionizing radiation reacting with silicon in a radiological environment, radiation hardening of CMOS devices is being actively investigated. If a radiation-tolerant IC (RTIC) is designed, it is very important to examine the design possibility of an application specific IC (ASIC) that uses a radiation-tolerant MOS field-effect transistor (MOSFET). This study developed a new RTIC design using an I-gate structure that is more effective in terms of time, cost, and reliability than the existing RTMOSFET. Because an RTIC with an I-gate structure can be fabricated via the usual full-custom IC design process, it can be produced after its reliability is ensured based on post-layout simulation results, which are obtained by layout parasitic extraction (LPE). To realize the possibility of such fabrication, radiation-tolerant digital and analog ICs were designed and fabricated in the standard 0.18- $\mu \text{m}$ CMOS process, and an irradiation test was conducted up to a total dose of approximately 2 Mrad. Accordingly, the radiation damage in the standard IC and the radiation tolerance of the RTIC were identified. Consequently, we have proposed and verified an efficient radiation-tolerant ASIC design solution.

Gate-Level Validation of Integrated Circuits With Structured-Illumination Read-Out of Embedded Optical Signatures

The integrated circuit (IC) chips are essential components in a variety of computing systems ranging from consumer electronics to high-security military devices. Hence, the authenticity of ICs is crucial. The pervasive nature of ICs and the need for their low-cost production has led to the globalization of IC design and manufacturing process, which has raised various security concerns including; (i) malicious tampering of ICs during fabrication to include Hardware Trojans (HT); and (ii) IC counterfeiting. To detect HTs and IC counterfeiting, we require an examination method to ensure the manufactured IC is consistent with the intended design. Here, we present a robust, rapid, and nondestructive IC authentication technique, which relies on imaging the optical watermarks embedded in predetermined locations in the IC. The watermark is a combination of unique signatures in the optical farfield reflection pattern created by modifying the physical layout of logic gates. These high-contrast optical signatures are enabled by embedding an innovative combination of plasmonic nanoantennas and grating structures directly in the metal-1 layer of the gate design. The uniqueness of logic gates' optical signatures is ensured through different plasmonic nanoantenna dimensions and periodicity of the surrounding gratings. For the rapid read-out of the watermarks, we present a confocal dark-field imaging technique utilizing modulated structured-illumination and lock-in signal acquisition. By combining these innovations in plasmonic nanoantennas and optical imaging, we demonstrate through numerical simulations a 30-fold contrast in polarization dependent reflectivity for each embedded optical signature allowing rapid read-out of watermarks and direct authentication of the IC design.

Genetic Algorithm-based Reliability Optimization for High-Level Synthesis

Soft errors (SEs) are a type of transient errors in integrated circuits (ICs) caused by radiation effects in the chips. They have become the major concern in IC design process in each CMOS technology generation since the decrease in supply voltage levels for shrinking transistor sizes makes the circuits more vulnerable than before. Previous studies generally use hardware redundancy for combinational circuits and error correcting codes for memory elements to mitigate or eliminate the SEs. However, adding extra hardware in final design may not always be possible if the design has tight area constraints. Different implementations of the same function may have different soft error rates (SERs) due to their error masking capabilities. Therefore, we can obtain various versions of the same function with different area, latency, and reliability values. Allocating the best resources to the operations of the design under area and latency constraints to optimize the overall system reliability has NP-complete time complexity. Evolutionary computing-based methods suit very well for this optimization problem. Motivated by this fact, in this paper, we present a genetic algorithm (GA)-based design method to increase the reliability of application-specific integrated circuits (ASICs). In this method, we use different versions of the same resources, each having a different area, latency, and reliability values. The goal of the GA-based optimizer is to allocate the best available resources to the application nodes to maximize the reliability of the design under tight area and latency constraints. Our experimental results show that we achieve up to 20.86% reliability improvement against a heuristic method with no additional area overhead. In order to further increase the reliability of the final design, we also propose a heuristic-based post-processing method, which adds duplicate resources to the final design without violating the constraint.

Guest Editors’ Introduction: Emerging Challenges and Solutions in SoC Verification

Verification has been one of the major bottlenecks in integrated circuit design process, which is exacerbated by the sheering design complexities nowadays. The increased design size is only one dimension of the growing complexities. Recent System-on-Chips (SoC) often feature multiple heterogeneous embedded processors and accelerators. While the heterogeneous architecture is more power efficient, it adds verification complexities of the hardware/software interaction and interconnect coherency. It is common that tens or hundreds of IP blocks, among which analog IPs occupy an increasing portion, are integrated into a single chip. Moreover, the growing market shares of devices for Internet-of-Things (IoT) and automotive applications have signified the requirements for verifying security and safety, which adds new dimensions to the complexities. As a result, the industry has encountered emerging challenges for correctly verifying increasingly complex SoCs in a timely manner, which create the “verification gap.” This special issue is devoted to address the verification challenges, the needs for advanced verification technologies to close the gap, and the state-of-the-art solutions.

Vulnerability Analysis of a Circuit Layout to Hardware Trojan Insertion

While the horizontal integrated circuit design process is extensively practiced, untrusted foundries can impose significant threats on the security of final products. A carefully inserted extra circuitry as a hardware trojan in a circuit layout can interfere with circuit functionality under very rare circumstances with inconsiderable footprints. In this paper, we introduce a novel layout-level vulnerability analysis flow to evaluate the susceptibility of a circuit layout’s regions to hardware Trojan insertion. We also present several metrics based on a circuit layout to quantify the possibility of hardware Trojan insertion in a specific region of layout. Results of applying our flow to several benchmarks have revealed considerably high vulnerability of circuit layouts to hardware Trojan insertion. Furthermore, several Trojans are implemented and inserted in layout regions with different vulnerabilities to evaluate the effectiveness of our new metrics. Our novel layout-level vulnerability analysis flow makes it possible to quantitatively determine the vulnerability of different implementations of a circuit and analyze the susceptibility of each corner of circuit layout to different types of functional Trojans.

Automated Routing for VLSI: Kuh's Group Contributions

EDA (Electronic Design Automation) industry is now a multibillion dollar business and numerous commercial and university tools exist to automatically solve various sub-problems of the IC (integrated circuit) design process. Many of the underlying ideas of the algorithms implemented in those programs originated in Professor Ernest Kuh's research group at UC Berkeley. The objective of this paper is to trace Kuh's group contributions to EDA , to bring attention to this group's many accomplishments in physical design area and to show the effects that the ideas which originated in Kuh's group have had on researchers throughout the years. We limit our attention to routing problems only.

Electrical Overstress of Integrated Circuits

Common misconceptions regarding electrical overstress (EOS) and the failure characteristics of integrated circuits (ICs) are summarized, analyzed and clarified. In order to avoid EOS fails right from the beginning of the IC design process, a methodology is proposed that accounts for the special characteristics of ICs and their applications in order to deal with EOS in the design, handling and application of ICs.

INTEGRATED CIRCUIT CHANNEL ROUTING USING A PARETO-OPTIMAL GENETIC ALGORITHM

An important part of the integrated circuit design process is the channel routing stage, which determines how to interconnect components that are arranged in sets of rows. The channel routing problem has been shown to be NP-complete, thus this problem is often solved using genetic algorithms. The traditional objective for most channel routers is to minimize total area required to complete routing. However, another important objective is to minimize signal propagation delays in the circuit. This paper describes the development of a genetic channel routing algorithm that uses a Pareto-optimal approach to accommodate both objectives. When compared to the traditional channel routing approach, the new channel router produced layouts with decreased signal delay, while still minimizing routing area.

ISFET characteristics in CMOS and their application to weak inversion operation

Design and fabrication of ISFETs in an unmodified CMOS process is presented to identify the main factors modifying the intrinsic characteristics of the MOSFET from which it is made and derive a model for its operation and pH sensitivity in weak inversion. Specifically trapped charge in the passivation layer and passivation capacitance introduced due to the method of fabrication have been identified and measured in a commercial 0.25 μ m CMOS process. Functional operation in weak inversion is shown, for sensor operation using extremely low currents and therefore low power, as well as enabling it to become an inherent part of the CMOS integrated circuit design process allowing creation of building blocks for biochemical VLSI systems.

Controlled on-chip heat transfer for directed heating and temperature reduction

Accurate thermal modeling is critical to address the heating-related problems in integrated circuits, as well as to ensure as-designed operation or to obtain performance predictions in a range of different operating conditions. We present our experimental and theoretical work on modeling thermal behavior in integrated circuits (ICs) at the resolution of single material layers. Through measurements and simulations we find that lateral metal interconnect networks have minimal effect on directing heat flow in bulk technologies, but may be more influential in SOI systems. Thermal via structures are effective for temperature reduction in either case. With this approach we are able to contribute to the IC design process by suggesting metal layout features for cooling and controlled heating.

Predictions of CMOS compatible on-chip optical interconnect

Interconnect has become a primary bottleneck in the integrated circuit design process. As CMOS technology is scaled, the design requirements of delay, power, bandwidth, and noise due to the on-chip interconnects have become more stringent. New design challenges are continuously emerging, such as delay uncertainty induced by process and environmental variations. It has become increasingly difficult for conventional copper interconnect to satisfy these design requirements. On-chip optical interconnect has been considered as a potential substitute for electrical interconnect. In this paper, predictions of the performance of CMOS compatible optical devices are made based on current state-of-the-art optical technologies. Electrical and optical interconnects are compared for various design criteria based on these predictions. The critical dimensions beyond which optical interconnect becomes advantageous over electrical interconnect are shown to be approximately one-tenth of the chip edge length at the 22 nm technology node.

VHDL modeling and model testing for DSP applications

The use of hardware description language models is now central to the digital design process. These models represent the initial interpretation of the specification. They are also used as input to synthesis tools in the application-specific integrated circuit design process central to the development of digital signal processor circuits. In this paper, the use of high-level graphics-based modeling tools is advocated to relieve the modeler of the burden of hand coding the models. A similar approach is advocated for developing test benches that test the models. Models and test benches are refined in a library structure. Environmental data generators are used to prepare test files to be read by the test benches. The test benches are linked directly to the specification and test plans control the test bench configuration. This approach is applied to infrared search and track and synthetic aperture radar systems.

An automata-theoretic approach to behavioral equivalence

Formal verification methods are used in the integrated circuit design process to guarantee equivalence between circuit specifications and implementations at the same or differing levels of abstraction. Equivalence checking between two finite-state automata or two combinational logic circuits is precisely defined and supported by a body of theoretical work. Algorithms that can determine the equivalence of large sequential and combinational logic circuits exist, and are in use today. In contrast, verifying that a logic-level description correctly implements a behavioral specification is considerably less developed. One major hindrance toward a precise notion of behavioral verification has been that parallel, serial or pipelined implementations of the same behavioral description can be implemented in finite-state automata with different input/output behaviors. In this paper, we use ϵ-moves to model the degree freedom that is afforded parallelism in a behavioral description that also contains complex control. Given some assumptions, we show how the set of finite automata derivable from a behavioral description can be presented compactly as an input-programmed automaton ( p-Automaton). The p-Automaton is named such due to the fact that during its derivation, we program meta-input variables in the p-Automaton that are not present in the original description. The logic-level implementation is deemed to be equivalent to the behavioral description if and only if the p-Automaton is equivalent to the logic-level finite automaton under some assignment to the meta-input variables. The above method allows for extending the use of finite-state automatan equivalence-checking algorithms to the problem of behavioral verification. It is particularly useful for verifying descriptions with a moderate amount of parallelism and complex control. We present experimental results obtained using our approach.

Silicon compilation: The future is now: Silicon compilers liberate the integrated circuit design process

Agreat deal of interest has recently been generated about a new integrated circuit (IC) design methodology called silicon compilation. Silicon compilation allows IC designers and system experts to quickly develop sure-fire, sophisticated, application-specific ICs with silicon efficiencies approaching those of handcrafted ICs.

Selecting a Color Monitor for an Interactive Graphics System used to Design Integrated Circuits

This paper describes the analysis and evaluation procedures used to select a color monitor for an interactive graphics system that designs integrated circuits. The analysis had five steps. First, users of a current black-and-white system were surveyed to define their needs and desires for a next-generation color interactive graphics system. Second, the most important monitor specifications and corresponding display quality factors, relative to the needs of the users, were determined. Third, a comparative analysis of 13-inch (33.02-cm) and 19-inch (48.26-cm) monitors was used to determine which size best filled overall system and user needs. Fourth, several off-the-shelf, 19-inch, high-resolution monitors were evaluated and the two best candidates were chosen. Fifth and last, a side-by-side human factors analysis was conducted using the two chosen displays, and the final monitor was selected. This recommended monitor has been integrated into all new interactive graphics terminals used to design integrated circuits, and operators have found the multicolored, high-quality image an effective and efficient tool for use in the integrated circuit design process.