Integrated Logic Circuits Research Articles

ANALYSIS AND IMPLEMENTATION OF CRYPTOGRAPHIC HASH FUNCTIONS IN PROGRAMMABLE LOGIC DEVICES / KRIPTOGRAFINIŲ MAIŠOS FUNKCIJŲ ĮGYVENDINIMO PROGRAMUOJAMOSIOS LOGIKOS LUSTUOSE TYRIMAS

In this day’s world, more and more focused on data protection. For data protection using cryptographic science. It is also important for the safe storage of passwords for this uses a cryptographic hash function. In this article has been selected the SHA-256 cryptographic hash function to implement and explore, based on fact that it is now a popular and safe. SHA-256 cryptographic function did not find any theoretical gaps or conflict situations. Also SHA-256 cryptographic hash function used cryptographic currencies. Currently cryptographic currency is popular and their value is high. For the measurements have been chosen programmable logic integrated circuits as they less efficiency then ASIC. We chose Altera Corporation produced prog-rammable logic integrated circuits. Counting speed will be investigated by three programmable logic integrated circuit. We will use programmable logic integrated circuits belong to the same family, but different generations. Each programmable logic integrated circuit made using different dimension technology. Choosing these programmable logic integrated circuits: EP3C16, EP4CE115 and 5CSEMA5F31. To compare calculations perfor-mances parameters are provided in the tables and graphs. Research show the calculation speed and stability of different programmable logic circuits. Vis daugiau dėmesio skiriama duomenų apsaugai – duomenų apsaugai skirta net atskira kriptografijos mokslo šaka. Taip pat yra svarbi slaptažodžių sauga, kurioje naudojamos kriptografinės maišos funkcijos. Darbe parinkta įgyvendinimui ir ištirta šiuo metu populiari bei saugi SHA-2 kriptografinė maišos funkcija. Ji naudojama kriptografinėse valiutose. SHA-2 kriptografinės funkcijos analizės metu nepavyko rasti teorinių spragų ar kolizijos atvejų. Tyrimams pasirinkti Altera programuojamos logikos integriniai grandynai, kurie efektyvumu nusileidžia tik specializuotiems integriniams grandynams. Skaičiavimo sparta ir stabilumas buvo tiriama trijuose programuojamos logikos integrinuose grandynuose, priklausančiuose tai pačiai šeimai ir pagamintais skirtingų kartų technologijomis – naudojant 65 nm, 60 nm ir 28 nm KMOP technologijas. Tirtų grandynų kodiniai žymenys EP3C16, EP4CE115 ir 5CSEMA5F31.

All Screen-Printed Logic Gates Based on Organic Electrochemical Transistors

We report on the fabrication and characterization of entirely screen-printed integrated logic circuits based on organic electrochemical transistors on flexible poly(ethylene terephthalate) (PET) substrates. The transistors are based on poly(3,4-ethylenedioxithiophene) poly(styrenesulfonate) and operate at a voltage of 1.5 V. Together with screen-printed resistors, the printed transistors were used as the building blocks for inverters, NAND gates, flip-flops, and a 2-b shift register. Dynamic characterizations of these logic gates need only five different inks that reveal a high reproducibility of the measured devices’ output signals. These results clearly indicate the high uniformity and reproducibility of the screen-printed transistors and resistors, emphasizing their applicability for integrated circuitry.

Benchmarking of Beyond-CMOS Exploratory Devices for Logic Integrated Circuits

A new benchmarking of beyond-CMOS exploratory devices for logic integrated circuits is presented. It includes new devices with ferroelectric, straintronic, and orbitronic computational state variables. Standby power treatment and memory circuits are included. The set of circuits is extended to sequential logic, including arithmetic logic units. The conclusion that tunneling field-effect transistors are the leading low-power option is reinforced. Ferroelectric transistors may present an attractive option with faster switching delay. Magnetoelectric effects are more energy efficient than spin transfer torque, but the switching speed of magnetization is a limitation. This article enables a better focus on promising beyond-CMOS exploratory devices.

Hybrid Flexible Resistive Random Access Memory-Gated Transistor for Novel Nonvolatile Data Storage.

Here, a single-device demonstration of novel hybrid architecture is reported to achieve programmable transistor nodes which have analogies to flash memory by incorporating a resistive switching random access memory (RRAM) device as a resistive switch gate for field effect transistor (FET) on a flexible substrate. A high performance flexible RRAM with a three-layered structure is fabricated by utilizing solution-processed MoS2 nanosheets sandwiched between poly(methyl methacrylate) polymer layers. Gate coupling with the pentacene-based transistor can be controlled by the RRAM memory state to produce a nonprogrammed state (inactive) and a programmed state (active) with a well-defined memory window. Compared to the reference flash memory device based on the MoS2 floating gate, the hybrid device presents robust access speed and retention ability. Furthermore, the hybrid RRAM-gated FET is used to build an integrated logic circuit and a wide logic window in inverter logic is achieved. The controllable, well-defined memory window, long retention time, and fast access speed of this novel hybrid device may open up new possibilities of realizing fully functional nonvolatile memory for high-performance flexible electronics.

Digital data transmission system with capacitive coupling for in-situ temperature sensing in lithium ion cells

Precise temperature measurement within a narrow time frame is crucial for the safe operation of Li-Ion battery cells. This paper proposes a digital approach for in-situ cell temperature measurement, relying on capacitive coupled data transmission between the controller in a cell and an external controller. In contrast to purely analog solutions, the digital approach satisfies all requirements in terms of electrochemical, space and transmission quality. For this purpose, analog and digital conceptual hardware setups were implemented for comparison and extensive measurements were carried out. The experimental results for the digital implementation show the influence of capacitor sizes and baud rates, providing a guideline for transmission rates for different sizes of cells. The paper also discusses in detail integration aspects for the digital approach. From the digital concept setup, valuable information is deduced regarding the communication latency, achievable energy consumption and miniaturization potential: Depending on the employed sampling rate, the transmission duration for one message with five temperature values can be reduced to as little as 65μs with a power consumption in the μW range. The proposed miniaturization enables an efficient, low cost, fully integrated logic circuit for data collection and transmission with a size not bigger than 2mm×3mm.

Central wavelength adjustment of light emitting source in interferometric sensors based on fiber-optic Bragg gratings

The paper is focused on the investigation of fiber-optic interferometric sensor based on the array of fiber Bragg gratings. Reflection spectra displacement mechanism of the fiber Bragg gratings under the external temperature effects and the static pressure is described. The experiment has shown that reflection spectra displacement of Bragg gratings reduces the visibility of the interference pattern. A method of center wavelength adjustment is proposed for the optical radiation source in accord ance with the current Bragg gratings reflection spectra based on the impulse relative modulation of control signal for the Peltier element controller. The semiconductor vertical-cavity surface-emitting laser controlled by a pump driver is used as a light source. The method is implemented by the Peltier element controller regulating and stabilizing the light source temperature, and a programmable logic-integrated circuit monitoring the Peltier element controller. The experiment has proved that the proposed method rendered possible to regulate the light source temperature at a pitch of 0.05 K and adjust the optical radiation source center wavelength at a pitch of 0.05 nm. Experimental results have revealed that the central wavelength of the radiation adjustment at a pitch of 0.005 nm gives the possibility for the capacity of the array consisting of four opticalfiber sensors based on the fiber Bragg gratings. They are formed in one optical fiber under the Bragg grating temperature change from 0° C to 300° C and by the optical fiber mechanical stretching by the force up to 2 N.

Formation CMOS Schemes on GaAs with Self-Aligned Nitride and Silicide Gates

Advanced integrated logic circuits on GaAs are mainly based on the using of n-channel field-effect transistors with gate Schottky (MESFET). To create the complementary MESFET integrated circuits the main problem is quite small Schottky barrier height (< 0,5 eV) on p-type gallium arsenide. One way to solve this problem is to use a nitride or silicide tungsten compounds to form gates given the thickness and composition.
 This paper highlights the features of the formation of complementary high-speed logic circuits on the p-GaAs with self-aligned gate based on nitride or silicide of tungsten obtained by reduced pressure horizontal reactor "Izotron 4" and of RF magnetron sputtering equipment "Oratorio-5." This technology can also be used to form a Schottky contact to n- channel MESFET.
 Since the manufacturing process of MESFET self-aligned gate provides using refractory gate material as a mask for the multiply ion implantation, the Schottky contact must withstand subsequent high-temperature heat treatment required to activate implanted impurities. In this connection, the action of high-temperature photonic and resistive heating on the barrier height of Schottky contact formed by nitride (silicide) tungsten (WNx, WSix) GaAs was also studied.

Boolean-logic-based nano-platform for competitive detection of biomacromolecules, surfactants, and explosives

We introduce a competitive strategy based on gold nanoparticles (AuNPs) to construct a nano-platform for sensing negatively charged analytes (NCA), including biomacromolecules, surfactants, and explosives. This approach is based on the competitive binding between NCA and AuNPs to positively charged coralyne. In the presence of NCA, the electrostatic attraction between NCA and coralyne is stronger than AuNPs binding to coralyne. The competitive interactions are programmable and can be utilized to regulate the absorbance and solution color of AuNPs via Boolean logic (such as YES, NOT, OR, INHIBIT, IMPLICATION logic gates). These integrated logic circuits are constructed based on dispersion-dominated AuNPs sensing progress, which avoids false results generated from the aggregation-dominated AuNPs sensor. The new concept of Boolean-logic-based nano-platform may find applications in a wide range of biological digital diagnosis and practical environmental applications and extend to further development of molecular computing circuits.

Chemically-driven “molecular logic circuit” based on osmium chromophore with a resettable multiple readout

Resettable molecular processing of inputs (Cu2+/H2O and F−/H+) to yield discriminating outputs and subsequent integration of logic circuits.

A compact, all-optical, THz wave generator based on self-modulation in a slab photonic crystal waveguide with a single sub-nanometer graphene layer.

We design a compact, all-optical THz wave generator based on self-modulation in a 1-D slab photonic crystal (PhC) waveguide with a single sub-nanometer graphene layer by using enhanced nonlinearity of graphene. It has been shown that at the bandgap edge of higher bands of a 1-D slab PhC, through only one sub-nanometer graphene layer we can obtain a compact, high modulation factor (about 0.98 percent), self-intensity modulator at a high frequency (about 0.6 THz) and low threshold intensity (about 15 MW per square centimeter), and further a compact, all-optical THz wave generator by integrating the self-modulator with a THz photodiode or photonic mixer. Such a THz source is expected to have a relatively high efficiency compared with conventional sources based on optical methods. The proposed THz source can find wide applications in THz science and technology, e.g., in THz imaging, THz sensors and detectors, THz communication systems, and THz optical integrated logic circuits.

Regaining Trust in VLSI Design: Design-for-Trust Techniques

Designers use third-party intellectual property (IP) cores and outsource various steps in their integrated circuit (IC) design flow, including fabrication. As a result, security vulnerabilities have been emerging, forcing IC designers and end-users to reevaluate their trust in hardware. If an attacker gets hold of an unprotected design, attacks such as reverse engineering, insertion of malicious circuits, and IP piracy are possible. In this paper, we shed light on the vulnerabilities in very large scale integration (VLSI) design and fabrication flow, and survey design-for-trust (DfTr) techniques that aim at regaining trust in IC design. We elaborate on four DfTr techniques: logic encryption, split manufacturing, IC camouflaging, and Trojan activation. These techniques have been developed by reusing VLSI test principles.

Current Switching in Graphene Quantum Point Contacts

Graphene has high-quality transport properties, but currents in graphene ribbons cannot be switched OFF, because of the absence of a bandgap. This is the most important obstacle for the use of graphene in the fabrication of integrated logic circuits. Here, we study current switching in zigzag graphene quantum point contacts using tight-binding Hamiltonians and the nonequilibrium Green function method. The current in these quantum point contacts is controlled by a back-gate and a top-gate potential. Our results show that the current can be effectively switched OFF for a potential range of 0.6 V. We explain this effect by computing the energy-band structure corresponding to the various regions of the quantum point contact. We show that these regions do not have a common conducting channel in a sufficiently large energy range and this results in zero conductance for energies in this range.

Boolean logic tree of graphene-based chemical system for molecular computation and intelligent molecular search query.

The most serious, and yet unsolved, problem of constructing molecular computing devices consists in connecting all of these molecular events into a usable device. This report demonstrates the use of Boolean logic tree for analyzing the chemical event network based on graphene, organic dye, thrombin aptamer, and Fenton reaction, organizing and connecting these basic chemical events. And this chemical event network can be utilized to implement fluorescent combinatorial logic (including basic logic gates and complex integrated logic circuits) and fuzzy logic computing. On the basis of the Boolean logic tree analysis and logic computing, these basic chemical events can be considered as programmable "words" and chemical interactions as "syntax" logic rules to construct molecular search engine for performing intelligent molecular search query. Our approach is helpful in developing the advanced logic program based on molecules for application in biosensing, nanotechnology, and drug delivery.

Logic Control of Enzyme-Like Gold Nanoparticles for Selective Detection of Lead and Mercury Ions

Functional logic gates based on lead ions (Pb(2+)) and mercury ions (Hg(2+)) that induce peroxidase-like activities in gold nanoparticles (Au NPs) in the presence of platinum (Pt(4+)) and bismuth ions (Bi(3+)) are presented. The "AND" logic gate is constructed using Pt(4+)/Pb(2+) as the input and the peroxidase-like activity of the Au NPs as the output; this logic gate is denoted as "Pt(4+)/Pb(2+)(AND)-Au NPPOX". When Pt(4+) and Pb(2+) coexist, strong metallophilic interactions (between Pt and Pb atoms/ions) and aurophilic interactions (between Au and Pb/Pt atoms/ions) result in significant increases in the deposition of Pt and Pb atoms/ions onto the Au NPs, leading to enhanced peroxidase-like activity. The "INHIBIT" logic gate is fabricated by using Bi(3+) and Hg(2+) as the input and the peroxidase-like activity of the Au NPs as the output; this logic gate is denoted as "Bi(3+)/Hg(2+)(INHIBIT)-Au NPPOX". High peroxidase-like activity of Au NPs in the presence of Bi(3+) is a result of the various valence (oxidation) states of Bi(3+) and Au (Au(+)/Au(0)) atoms on the nanoparticle's surface. When Bi(3+) and Hg(2+) coexist, strong Hg-Au amalgamation results in a large decrease in the peroxidase-like activity of the Au NPs. These two probes (Pt(4+)/Pb(2+)(AND)-Au NPPOX and Bi(3+)/Hg(2+)(INHIBIT)-Au NPPOX) allow selective detection of Pb(2+) and Hg(2+) down to nanomolar quantities. The practicality of these two probes has been validated by analysis of Pb(2+) and Hg(2+) in environmental water samples (tap water, river water, and lake water). In addition, an integrated logic circuit based on the color change (formation of reddish resorufin product) and generation of O2 bubbles from these two probes has been constructed, allowing visual detection of Pb(2+) and Hg(2+) in aqueous solution.

PROBABILISTIC TRANSFER MATRIX WITH MIXED BINARY-DECIMAL CODING FOR LOGIC CIRCUIT RELIABILITY ANALYSIS

Technology scale leads to increasing the vulnerability of new integrated logic circuits. The high-energy neutrons (present in terrestrial cosmic radiation) and alpha particles (that originate from impurities in the packaging materials) play important role in occurrence of transient faults which are effective factor for designing reliable integrated circuits. Thus, a fast and scalable method to obtain accurate reliability value is an issue to have a dependable logic circuit design. In this paper, a new fast and scalable method is proposed to calculate the circuit reliability in which the effects of nested reconvergent paths, as a main source of inaccuracy, is considered. In the presence of reconverging signals a binary probability matrix is used to resolve signals correlation problem and increase the accuracy of the obtained reliability. Also a new mixed binary-decimal code allocation is proposed to increase the scalability of the method and reduce the complexity of calculation. Simulation results show that our proposed solution is a fast method with less complexity and also gives an accurate reliability value in comparison with other methods.

Toward Printed Integrated Circuits based on Unipolar or Ambipolar Polymer Semiconductors

For at least the past ten years printed electronics has promised to revolutionize our daily life by making cost-effective electronic circuits and sensors available through mass production techniques, for their ubiquitous applications in wearable components, rollable and conformable devices, and point-of-care applications. While passive components, such as conductors, resistors and capacitors, had already been fabricated by printing techniques at industrial scale, printing processes have been struggling to meet the requirements for mass-produced electronics and optoelectronics applications despite their great potential. In the case of logic integrated circuits (ICs), which constitute the focus of this Progress Report, the main limitations have been represented by the need of suitable functional inks, mainly high-mobility printable semiconductors and low sintering temperature conducting inks, and evoluted printing tools capable of higher resolution, registration and uniformity than needed in the conventional graphic arts printing sector. Solution-processable polymeric semiconductors are the best candidates to fulfill the requirements for printed logic ICs on flexible substrates, due to their superior processability, ease of tuning of their rheology parameters, and mechanical properties. One of the strongest limitations has been mainly represented by the low charge carrier mobility (μ) achievable with polymeric, organic field-effect transistors (OFETs). However, recently unprecedented values of μ ∼ 10 cm(2) /Vs have been achieved with solution-processed polymer based OFETs, a value competing with mobilities reported in organic single-crystals and exceeding the performances enabled by amorphous silicon (a-Si). Interestingly these values were achieved thanks to the design and synthesis of donor-acceptor copolymers, showing limited degree of order when processed in thin films and therefore fostering further studies on the reason leading to such improved charge transport properties. Among this class of materials, various polymers can show well balanced electrons and holes mobility, therefore being indicated as ambipolar semiconductors, good environmental stability, and a small band-gap, which simplifies the tuning of charge injection. This opened up the possibility of taking advantage of the superior performances offered by complementary "CMOS-like" logic for the design of digital ICs, easing the scaling down of critical geometrical features, and achieving higher complexity from robust single gates (e.g., inverters) and test circuits (e.g., ring oscillators) to more complete circuits. Here, we review the recent progress in the development of printed ICs based on polymeric semiconductors suitable for large-volume micro- and nano-electronics applications. Particular attention is paid to the strategies proposed in the literature to design and synthesize high mobility polymers and to develop suitable printing tools and techniques to allow for improved patterning capability required for the down-scaling of devices in order to achieve the operation frequencies needed for applications, such as flexible radio-frequency identification (RFID) tags, near-field communication (NFC) devices, ambient electronics, and portable flexible displays.

Selective Flexibility: Creating Domain-Specific Reconfigurable Arrays

Historically, hardware acceleration technologies have either been application-specific, therefore lacking in flexibility, or fully programmable, thereby suffering from notable inefficiencies on an application-by-application basis. To address the growing need for domain-specific acceleration technologies, this paper describes a design methodology (i) to automatically generate a domain-specific coarse-grained array from a set of representative applications and (ii) to introduce limited forms of architectural generality to increase the likelihood that additional applications can be successfully mapped onto it. In particular, coarse-grained arrays generated using our approach are intended to be integrated into customizable processors that use application-specific instruction set extensions to accelerate performance and reduce energy; rather than implementing these extensions using application-specific integrated circuit (ASIC) logic, which lacks flexibility, they can be synthesized onto our reconfigurable array instead, allowing the processor to be used for a variety of applications in related domains. Results show that our array is around 2× slower and 15× larger than an ultimately efficient ASIC implementation, and thus far more efficient than fieldprogrammable gate arrays (FPGAs), which are known to be 3-4× slower and 20-40× larger. Additionally, we estimate that our array is usually around 2× larger and 2× slower than an accelerator synthesized using traditional datapath merging, which has, if any, very limited flexibility beyond the design set of DFGs.

Vertically Integrated Logic Circuits Constructed Using ZnO-Nanowire-Based Field-Effect Transistors on Plastic Substrates

ZnO-nanowire-based logic circuits were constructed by the vertical integration of multilayered field-effect transistors (FETs) on plastic substrates. ZnO nanowires with an average diameter of -100 nm were synthesized by thermal chemical vapor deposition for use as the channel material in FETs. The ZnO-based FETs exhibited a high I(ON)/I(OFF) of > 10(6), with the characteristic of n-type depletion modes. For vertically integrated logic circuits, three multilayer FETs were sequentially prepared. The stacked FETs were connected in series via electrodes, and C-PVPs were used for the layer-isolation material. The NOT and NAND gates exhibited large logic-swing values of -93%. These results demonstrate the feasibility of three dimensional flexible logic circuits.

High-performance top-gated monolayer SnS2 field-effect transistors and their integrated logic circuits

Two-dimensional (2D) layered semiconductors are very promising for post-silicon ultrathin channels and flexible electronics due to the remarkable dimensional and mechanical properties. Besides molybdenum disulfide (MoS2), the first recognized 2D semiconductor, it is also important to explore the wide spectrum of layered metal chalcogenides (LMCs) and to identify possible compounds with high performance. Here we report the fabrication of high-performance top-gated field-effect transistors (FETs) and related logic gates from monolayer tin disulfide (SnS2), a non-transition metal dichalcogenide. The measured carrier mobility of our monolayer devices reaches 50 cm(2) V(-1) s(-1), much higher than that of the back-gated counterparts (~1 cm(2) V(-1) s(-1)). Based on a direct-coupled FET logic technique, advanced Boolean logic gates and operations are also implemented, with a voltage gain of 3.5 and output swing of >90% for the NOT and NOR gates, respectively. The superior electrical and integration properties make monolayer SnS2 a strong candidate for next-generation atomic electronics.

All Optical Logic Gates Based on Two Dimensional Plasmonic Waveguides with Nanodisk Resonators

In this paper, we propose, analyze and simulate the performances of some new plasmonic logic gates in two dimensional plasmonic waveguides with nanodisk resonators, using the numerical method of finite difference time domain (FDTD). These gates, including XOR, XNOR, NAND, and NOT, can provide the highly integrated optical logic circuits. Also, by cascading and combining these basic logic gates, any logic operation can be realized. These devices can be utilized significantly in optical processing and telecommunication devices.