Integrated Circuit Form Research Articles

High performance accelerators for deep neural networks: A review

AbstractThe availability of huge structured and unstructured data, advanced highly dense memory and high performance computing machines have provided a strong push for the development in artificial intelligence (AI) and machine learning (ML) domains. AI and machine learning has rekindled the hope of efficiently solving complex problems which was not possible in the recent past. The generation and availability of big‐data is a strong driving force for the development of AI/ML applications, however, several challenges need to be addressed, like processing speed, memory requirement, high bandwidth, low latency memory access, and highly conductive and flexible connections between processing units and memory blocks. The conventional computing platforms are unable to address these issues with machine learning and AI. Deep neural networks (DNNs) are widely employed for machine learning and AI applications, like speech recognition, computer vison, robotics, and so forth, efficiently and accurately. However, accuracy is achieved at the cost of high computational complexity, sacrificing energy efficiency and throughput like performance measuring parameters along with high latency. To address the problems of latency, energy efficiency, complexity, power consumption, and so forth, a lot of state of the art DNN accelerators have been designed and implemented in the form of application specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs). This work provides the state of the art of all these DNN accelerators which have been developed recently. Various DNN architectures, their computing units, emerging technologies used in improving the performance of DNN accelerators will be discussed. Finally, we will try to explore the scope for further improvement in these accelerator designs, various opportunities and challenges for the future research.

Kilowatt-Range Picosecond Switching Based on Microplasma Devices

Plasma formation in micro- and nano-scales enables an ultrahigh-dv/dt picosecond switching in an integrated circuit form factor. Such on-chip plasma devices could provide a transformative approach to achieving high-power levels at very high frequencies, far surpassing the best performance of conventional III-V electronics. In this work, we demonstrate the application of scaled-up nano- and microplasma switches as discrete devices in high-performance picosecond pulsed-power sources. A prototype circuit, utilizing the fabricated plasma devices operating as the switch, shows a high voltage-rising-rate beyond 10 kV ns <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> at 15 kW peak power. The pulsed-power source exhibits a sub-100 ps rise-time (without de-embedding). The device has the capability of reaching exceptionally high current densities up to 325 A mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> . The switches are compatible with planar semiconductor fabrication, enabling their integration with other electronic devices and microwave components, which opens pathways towards the future ultrahigh power density picosecond pulsed-power sources.

Learning automata based energy-efficient AI hardware design for IoT applications.

Energy efficiency continues to be the core design challenge for artificial intelligence (AI) hardware designers. In this paper, we propose a new AI hardware architecture targeting Internet of Things applications. The architecture is founded on the principle of learning automata, defined using propositional logic. The logic-based underpinning enables low-energy footprints as well as high learning accuracy during training and inference, which are crucial requirements for efficient AI with long operating life. We present the first insights into this new architecture in the form of a custom-designed integrated circuit for pervasive applications. Fundamental to this circuit is systematic encoding of binarized input data fed into maximally parallel logic blocks. The allocation of these blocks is optimized through a design exploration and automation flow using field programmable gate array-based fast prototypes and software simulations. The design flow allows for an expedited hyperparameter search for meeting the conflicting requirements of energy frugality and high accuracy. Extensive validations on the hardware implementation of the new architecture using single- and multi-class machine learning datasets show potential for significantly lower energy than the existing AI hardware architectures. In addition, we demonstrate test accuracy and robustness matching the software implementation, outperforming other state-of-the-art machine learning algorithms.This article is part of the theme issue ‘Advanced electromagnetic non-destructive evaluation and smart monitoring’.

Determination of Spectral Characteristics in a Vibration Sensor Microcircuit

This article discusses aspects of the implementation of digital signal processing algorithms in devices with multifunctional diagnostics of bearing assemblies in integrated-circuit form. The possibility of applying the effective implementation of spectral analysis algorithms on a defined basis is considered. The structural flow chart of the filter which performs Goertzel transformation and schemes for implementation of the fast Fourier transform unit is shown. To solve these problems in Matlab environment were developed mathematical models of Goertzel filter of fast Fourier transform unit was simulated operation of these units for specifying of parameters and evaluation of achieved characteristics. After the evaluation of simulation results, 2 types of spectral analysis units were developed: Goertzel transformation units for accurate calculations and fast Fourier transform units for analysis during the whole operating band. The created units of spectral analysis make it possible to efficiently solve the problems of bearing diagnostics, obtain information on the video spectrum of the vibration signal in the full frequency band and at the same time to determine the exact value or vibration levels at the characteristic frequencies.

A Front-End Amplifier With Current Compensation Feedback Input Impedance Booster for Neural Signal Applications

In integrated circuit form, the front-end amplifier (FEA) determines the fidelity of the biosignal detection, signal-to-noise ratio, power consumption and detector size for the future multi-channel neural signal recording systems and applications. Especially for the high-density implantable applications, a higher input impedance reduces the signal attenuation (with respect to the high-impedance miniature electrodes), and lowers the current into the tissue (to avoid the overheating damage). In this paper, an input impedance booster with current compensation feedback technique is proposed, it neutralizes any currents generated at input of FEA without affecting the gain. It substantially yields a high input impedance across process and device mismatches. The proposed front-end circuit is implemented on a $0.18\mu \text{m}$ CMOS process, it achieves an input impedance of approximately 60 $\text{G}\Omega $ , and CMRR of 61 dB with 57 dB PSRR. The input-referred noise is approximately $5.6~\mu \text{v}/\surd $ Hz while consuming $7.6~\mu \text{W}$ in 0. 025mm2chip area.

Partial fraction expansion–based realizations of fractional‐order differentiators and integrators using active filters

SummaryApproximations of the fractional‐order differentiator and integrator operators s±r are proposed in this work. These approximations target the realization of these operators using standard active filter transfer functions. Hence, circuit implementations in integrated circuit form or in discrete component form are significantly facilitated. Complementary metal‐oxide‐semiconductor (CMOS) realizations of the proposed approximations are given and validated via simulations using the AMS 0.35 μm CMOS technology, while experimental results using operational amplifier circuits are tested and confirm the proposed theory.

Note: A 102 dB dynamic-range charge-sampling readout for ionizing particle/radiation detectors based on an application-specific integrated circuit (ASIC).

An original technique for the measurement of charge signals from ionizing particle/radiation detectors has been implemented in an application-specific integrated circuit form. The device performs linear measurements of the charge both within and beyond its output voltage swing. The device features an unprecedented spectroscopic dynamic range of 102 dB and is suitable for high-resolution ion and X-γ ray spectroscopy. We believe that this approach may change a widespread paradigm according to which no high-resolution spectroscopy is possible when working close to or beyond the limit of the preamplifier's output voltage swing.

Design of the CCD-TCD2964BFG Drive and Sampling Based on FPGA

This technology is mainly focused on the charge coupled device (CCD)TCD2964BFG as image sensor and using AD9826 as sampling chip, which introduces a design of driving and sampling circuit based on the FPGA of Altera Corporation. It discusses the design of driving and control timing by using FPGA chip EP4CE30F23C7N technology. Then it describes the design of the CCD driver board and the CCD mounting board in detail. This is a pivotal design to high-precision measurement, color image scanning and so on. Its highest accuracy can be reached 4800DPI with high resolution when it works and its output signal can be more reliable, more stable by being processed by AD9826, so it is very important for high-precision measurement, color image scanning ,etc. While making it into sub-circuit board physical model by using integrated circuit form, meanwhile, it’s very convenient to connect with a variety of FPGA core boards and it can be applied on various occasions by outgoing interface signals. The design is known for its flexibility, high integration, easy to update, convenient to apply and so on. The observed results indicate that the design of driving timing and circuit can meet the normal demands for the color linear CCD.

Alternative of Bridge-Based Circuits for Differential Resistive Sensors

This paper presents an alternative approach to implement a signal conditioning circuit for measuring resistance relative changes of differential resistive sensors. The proposed analog circuit uses two operational conveyors and one operational amplifier (opamp) as active building blocks to produce an output voltage as a function of the relative change of the sensor. In comparison with the classic voltage-mode Wheatstone bridge (VMWB) configuration, the sensor relative change can be estimated by the proposed circuit without using any sensor reference resistor. Surpassing a current-mode Wheatstone bridge (CMWB) using second-generation current conveyors (CCIIs), the proposed configuration provides higher accuracy. Compared to existing mixed-mode configurations realized in integrated circuit form, the proposed circuit offers simpler construction. PSPICE simulation and experimental results are given to verify the effectiveness of the proposed circuit. Test results obtained by utilizing the implemented prototype for a commercial linear position sensor are also included.

A High Input Impedance Low Noise Integrated Front-End Amplifier for Neural Monitoring.

Within neural monitoring systems, the front-end amplifier forms the critical element for signal detection and pre-processing, which determines not only the fidelity of the biosignal, but also impacts power consumption and detector size. In this paper, a novel combined feedback loop-controlled approach is proposed to compensate for input leakage currents generated by low noise amplifiers when in integrated circuit form alongside signal leakage into the input bias network. This loop topology ensures the Front-End Amplifier (FEA) maintains a high input impedance across all manufacturing and operational variations. Measured results from a prototype manufactured on the AMS 0.35 [Formula: see text] CMOS technology is provided. This FEA consumes 3.1 [Formula: see text] in 0.042 [Formula: see text], achieves input impedance of 42 [Formula: see text], and 18.2 [Formula: see text] input-referred noise.

Back‐gate current neutralisation feedback loop for high‐input impedance neural FEAs

The front-end amplifier (FEA) for neural signal applications forms the critical element for signal detection and pre-processing, which determines not only the fidelity of the biosignal, but also impacts power consumption and detector size. A back-gate current neutralisation feedback technique is proposed to compensate for input leakage currents generated by low-noise amplifiers alongside signal leakage into the input bias network when in integrated circuit (IC) form. Significantly, this topology ensures the FEA maintains a high-input impedance across the wide range of manufacturing and operational variations seen in ICs.

P-Val: Antifuse-Based Package-Level Defense Against Counterfeit ICs

The rapidly growing incidences of counterfeit integrated circuits (ICs) pose a significant threat to the semiconductor industry. These ICs may suffer from functional, performance, or reliability issues and can affect chip manufacturers, system designers as well as end users. The standard chip/package level structural and functional tests are often inadequate in detecting various forms of counterfeit ICs. Moreover, existing design for security approaches are usually not attractive due to additional design modifications, hardware overhead, test cost, and inadequate robustness. In this paper, we propose a novel, low-overhead package-level IC integrity validation approach, referred to as P-Val, for unified protection against two primary forms of counterfeiting attacks: 1) recycling and 2) cloning. Protection against recycled/remarked chips is achieved through a unique active defense that inserts antifuses (AFs) (one-time programmable) to few select pins inside the package. It effectively disables the functionality or “locks” these pins, which need to be programmed before first-time use to make a chip functional in a system. To protect against cloned ICs, intrinsic random variations in programmed resistances of AFs connected to some of the remaining IC pins are exploited to create unique chip-specific signatures for authentication. P-Val requires no die-level design modifications and remains effective for legacy designs. Moreover, we show that it is effective for small chips with just few pins including analog ICs, where common authentication approaches fail to work. We discuss optimal choice of AF structure and program parameters; their integration in IC packages; and the signature generation/verification process. Through mathematical analysis and simulation results, we demonstrate that the proposed mechanism provides high level of protection against counterfeiting attacks at ultralow overhead (<0.05% package area).

Lasers in InP generic photonic integration technology platforms

Abstract A review is given of a number of lasers in a form of photonic integrated circuits realized on InP substrate using a generic integration approach. The potential of these photonic circuits lies in their compactness, low power consumption, and significant reduction of fabrication cost by realization in generic foundry runs. Generic integration platforms offer the possibility of realizing functionally advanced photonic circuits using combinations of just a few standardized and parameterized building blocks. This vibrant field opens new doors to innovative product development for SMEs as well as curiosity-driven research.

Monolithically integrated 2.5 GHz extended cavity mode-locked ring laser with intracavity phase modulators.

A mode-locked extended cavity quantum well ring laser at 1.58μm with a repetition rate of 2.5GHz in the form of a photonic integrated circuit is presented. The device is realized using InP-based active-passive integration technology. The 33mm long cavity contains gain, saturable absorption, and passive waveguide sections as well as phase shifter sections to enable fine tuning of the spectral position of the lasing modes. Passive and hybrid mode-locked operation, along with the wavelength tuning of the laser modes, are experimentally demonstrated. In the passive mode-locking regime, a beat signal at the fundamental round trip frequency with a 3dB bandwidth of 6.1kHz is produced on a fast photo diode.

Компенсация паразитных элементов транзистора с настройкой импедансов на гармониках в усилителе класса F

The authors present a new method of construction and calculation of the output load circuit (OLC) for class F power amplifiers (PA) with the addition of the third harmonic of the voltage. This method allows compensating the negative influences of parasitic elements of transistor (output capacitance — COUT, and inductance — LOUT) on the drain efficiency of the amplifier. The circuit of the parasitic elements was considered as a part of the proposed OLC. To calculate the OLC a system of three algebraic equations was compiled. The system is solved numerically relative to the three parameters of the OLC, for which the impedance on a chip of the transistor (on COUT) for odd and even harmonics corresponds to the theory of class F PAs. This method is applicable for the calculation of the OLC, which is realized in the frequency range of 300—500 MHz, where the use of elements with lumped parameters only is not always possible, while using elements with distributed parameters leads to a substantial increase in the size of the whole amplifier. In the developed OLC, the authors used elements with both lumped and distributed parameters, thus achieving a compromise between the geometric dimensions and physical realizability of the circuit elements. The proposed OLC, taking into account the parasitic elements of the transistor, allows setting impedances independently at the first and third harmonics while maintaining impedance at the second harmonic tending to zero. This makes it possible to optimize the drain efficiency at a given level of output power. The efficiency ?d = 72,5% was experimentally obtained at POUT = 1,045 W for the class F amplifier running at 400 MHz. The proposed methodology for constructing and calculating the OLC can be used to implement class F power amplifiers in the integrated-circuit form.

A proposed ultra low-noise optical receiver for 1.55 μm applications

A high-sensitivity optical receiver based on InP/InGaAs superlattice avalanche photodiode (SL-APD) followed by an InGaAs MESFET transimpedance pre-amplifier has been proposed for operation in 1.55 μm wavelength region. The proposed optical receiver may be realised in the hybrid integrated circuit form. The low excess-noise factor of the SL-APD significantly reduces the value of minimum detectable optical power and improves the sensitivity of the over all receiver. The proposed receiver has been analysed theoretically. The results of computation show that the device has a high transimpedance gain (∼60 dB-ohm) with a bandwidth of 11 GHz for a photodetector capacitance of 110 fF. The sensitivity of the receiver has been found to be (∼−27.3d Bm) at operating bit rate of 15 Gb/s for a bit-error-rate of 10−9. The performance of the receiver can be optimised in respect of transimpedance gain, bandwidth and sensitivity by following guidelines provided in this paper. The proposed photoreceiver outperforms the existing receivers based on p-i-n/FET or conventional APD/FET photoreceivers.

Optimised weighted-resistor digital to analogue converter

From the classical weighted-resistor (WR) digital to analogue converter (DAC), two-stage DACs are derived. Conditions for minimum spread and the minimum total resistance for the two-stage DACs are derived. The theory is extended to multistage WR DACs. Thus, an optimised WR DAC is obtained that has minimum spread and the minimum total resistance and is therefore, suitable for economic fabrication in integrated circuit form.

A pipelined subranging analogue-to-digital video convertor with time-interleaved sampling

Video analogie-to-digital convertors are mostly based on the subranging flash and two-step flash architectures owing to their reduced silicon area and power consumption, and also because their operating frequency can be easily extended towards higher frequencies through the adoption of either time-interleaved or pipelined techniques. In this paper an alternative subranging analogue-to-digital convertor architecture is proposed in which the time-interleaved and pipelined techniques are jointly employed in order to achieve further saving of the die area and allow more relaxed speed requirements of the comparators in the flash quantizers. For visiophony applications, with 8-bit resolution and 13·5 MHz conversion frequency, this convertor has been constructed in integrated circuit form using a 1·2 μm CMOS technology, yielding an active area of 2·18 mm 2 and a power consumption of 170 mW.

CCD arrays for readout of electrophotographic latent images

Arrays of charge sensing elements have been fabricated for nondestructive electronic readout of latent images on electrophotographic materials. The arrays are implemented in the form of a monolithic integrated circuit in which each sensing element is a 5- mu m *5- mu m MOS capacitor; 2048 such elements are arranged in a linear format with effective 5- mu m element-to-element pitch. On-chip circuitry allows for multiple sampling at each sensing site for enhancing signal-to-noise ratio. The resulting signals from the sense elements are multiplexed onto charge-coupled-device (CCD) shift registers for high-speed serial readout. To allow for the small sensor-to-film gap (on the order of 10 mu m) required for capacitive sensing, the chip's bond pads are recessed in deep grooves below the active array surface. The array is packaged within a hydrostatic air bearing which maintains a constant and uniform gap. The response of the array to targets of high spatial frequency recorded on various electrophotographic materials is in excellent agreement with analytical predictions.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

100-MHz monolithic low-pass filters with transmission zeros using NIC integrators

A monolithic method of implementing VHF filters with transmission zeros is presented. The transmission zeros are obtained using a modified leapfrog simulation method realized without floating capacitors that does not require summing circuits inside the feedback loops. The integrators used are balanced negative impedance converter (NIC) integrators with grounded capacitors, which do not require p-n-p transistors and are suited for low-voltage applications. A low-pass filter with a cutoff frequency of 100 MHz and with a transmission zero at 166 MHz designed and built in an integrated circuit form showed good results, confirming the feasibility of the method. >