Integrated Circuit Emphasis Research Articles

A Methodology to Assist in Improvements of Low-cost Electrical Impedance Tomography Systems

Electrical Impedance Tomography (EIT) is a technique that enables the reconstruction of the impedance distributions inside a vessel in a multiphase flow of industrial processes. Such a technique combines a data acquisition (DAQ) system to inject a current and to measure the voltages on the sensors and an inverse problem technique to reconstruct the image properly. This problem is highly ill-conditioned, causing errors to produce instabilities. Therefore, when performing the acquisition, the DAQ system must have adequate accuracy to allow the reconstruction of images with good quality. To avoid these measurement inaccuracies, this paper introduces a methodology that aid in the process of development of low-cost systems. It consists of investigating the errors in the current version of the system. Further, predicting the systematic errors of each subsystem by modeling its frequency response by Simulation Program with Integrated Circuit Emphasis (SPICE). From this information, it is possible to perform critical analysis, aiding design decisions.

Algorithms for building and operation modeling of large electrical circuits with memristor-diode crossbars in a biomorphic neuroprocessor

The biomorphic neuroprocessor is the hardware implementation of the impulse neural network in which incoming information from a set of numbers is converted into impulses, and outgoing information, on the contrary, from impulses into binary code. For the automatic building of electrical circuits of the input coding and output decoding units in neuroprocessor using ultra-large logic matrices based on a memristor-diode crossbar, appropriate algorithms have been developed. For the subsequent imitation modeling of information processing in these units, as well as in the memory matrix of the neuroprocessor, the algorithm for calculating large electrical circuits containing memristor-diode crossbars has been created. This simulation algorithm is based on the well-known algorithm of Simulation Program with Integrated Circuit Emphasis and includes original mathematical models of the memristor and the selective element of the Zener diode, as well as the algorithm for modeling the resistive switching of the memristor. The results of imitation modeling using the developed algorithms and corresponding programs showed the operability of the constructed electrical circuits of the input unit in the mode of encoding a binary number into a impulse frequency by a population of three neurons and the output unit of a neuroprocessor that decodes the impulses coming from neurons into binary format as well as the operability of the memory matrix under weighting and summing impulses. The created algorithms and programs package based on them can be used to effectively solve the engineering and technical problem of manufacturing a biomorphic neuroprocessor that requires modeling of information processing in individual neuroprocessor units based on large memristor-diode arrays in order to optimize their parameters.

Decision Support System in a Memristor-Based Mobile CIM Architecture Applied on Big Data Computation and Storage

Data computation and storage are essential parts of developing big data applications. The memristor device technology could remove the speed and energy efficiency bottleneck in the existing data processing. The present experimental work investigates the decision support system in a new architecture, computation-in-memory (CIM) architecture, which can be utilized to store and process big data in the same physical location at a faster rate. The decision support system is used for data computation and storage, with the aims of helping memory units read, write, and erase data and supporting their decisions under big data communication ambiguities. Data communication is realized within the crossbar by the support of peripheral controller blocks. The feasibility of the CIM architecture, adaptive read, write, and erase methods, and memory accuracy were investigated. The integrated circuit emphasis (SPICE) simulation results show that the proposed CIM architecture has the potential of improving the computing efficiency, energy consumption, and performance area by at least two orders of magnitude. CIM architecture may be used to mitigate big data processing limits caused by the conventional computer architecture and complementary metal-oxide-semiconductor (CMOS) transistor process technologies.

Stability- and Crosstalk-Based Performance of Multi- and Double-walled Mixed CNT Bundles as Interconnect for Next-Generation Technology Nodes

The temperature-dependent modeling technique (in the temperature range of 200–500[Formula: see text]K) for a mixed class of carbon nanotube (CNT) bundle interconnects is proposed. The equivalent single conductor (ESC) transmission line models of multi-walled carbon nanotube (MWCNT) and double-walled carbon nanotube (DWCNT) are combined to develop multiple single conductor (MSC) model of mixed CNT interconnects. Various possible arrangements of densely packed MWCNT and DWCNT bundles (MDCB) are considered to form different types of mixed CNT bundle structures (MDCB-1, MDCB-2, MDCB-3 and MDCB-4). The integrated circuit emphasis simulation is performed and the performances of these mixed CNT bundle interconnects are investigated in terms of propagation delay (with and without crosstalk), power dissipation, power-delay product (PDP). Switching times, overshoot voltages and Nyquist plots are analyzed to check the stability of these mixed CNT structures for global interconnect length for 32-nm, 22-nm and 16-nm technology nodes. It is observed that the MDCB-1 structure yields the most promising result in all aspects for interconnect applications in the near future.

Simulations of hybrid charge-sensing single-electron-transistors and CMOS circuits

Single-electron transistors (SETs) have been extensively used as charge sensors in many areas, such as quantum computations. In general, the signals of SETs are smaller than those of complementary metal–oxide–semiconductor (CMOS) devices, and many amplifying circuits are required to enlarge the SET signals. Instead of amplifying a single small output, we theoretically consider the amplification of pairs of SETs, such that one of the SETs is used as a reference. We simulate the two-stage amplification process of SETs and CMOS devices using a conventional SPICE (Simulation Program with Integrated Circuit Emphasis) circuit simulator. Implementing the pairs of SETs into CMOS circuits makes the integration of SETs more feasible because of direct signal transfer from the SET to the CMOS circuits.

Intelligent Detection Methods of Electrical Connection Faults in RF Circuits

Printed circuit boards (PCBs) have a large number of electrical connection nodes. Exposure to harsh environments may lead to connection faults in these nodes. In the present work, intelligent detection methods for electrical connection faults were studied. Specifically, the fault characteristics of connectors, bonding wires and solder balls in the frequency domain were analyzed. The reflection and transmission parameters of an example filter circuit with electrical connection faults were calculated using the Simulation Program with Integrated Circuit Emphasis (SPICE). With these obtained electrical parameters, three machine learning algorithms were used to detect example electrical connection faults for the example circuit. Based upon the performance evaluations of the three algorithms, one can conclude that machine-learning-based intelligent fault detection is a promising technique in diagnosing circuit faults due to electrical connection issues with high accuracy and lower time cost as compared to current manual processes.

Bandwidth extension method based on the field-shunting effect in a high-gain photoelectric receiver circuit.

In the high-gain photoelectric receiver circuit, the method based on the field-shunting effect is applied to improve the bandwidth of the transimpedance amplifier. This method is implemented by adding a ground trace under the gain resistor, which reduces the parasitic capacitance of the gain resistor and thus increases the bandwidth. To obtain the specific impact of this method on bandwidth, a series of simulations are carried out, including electromagnetic simulations of a three-dimensional structure of circuit gain part and simulation program with integrated circuit emphasis (SPICE) simulations of the high-gain voltage-current feedback transimpedance amplifier. Finally, the optimal simulation result shows that selecting a 1206 size chip fixed resistor and setting the ground trace width to 1.1 mm can greatly reduce the influence of resistor parasitic effects on the circuit, thereby achieving the best performance of bandwidth extension. Further, the comparative experiment also verifies the effectiveness of the method for bandwidth enhancement.

Fabrication, Characterization, and Modeling of an Aluminum Oxide-Gate Ion-Sensitive Field-Effect Transistor-Based pH Sensor.

The ion-sensitive field-effect transistor (ISFET) is a popular technology utilized for pH sensing applications. In this work, we have presented the fabrication, characterization, and electrochemical modeling of an aluminum oxide (Al2O3)-gate ISFET-based pH sensor. The sensor is fabricated using well-established metal–oxide–semiconductor (MOS) unit processes with five steps of photolithography, and the sensing film is patterned using the lift-off process. The Al2O3 sensing film is deposited over the gate area using pulsed-DC magnetron-assisted reactive sputtering technique in order to improve the sensor performance. The material characterization of sensing film has been done using x-ray diffraction, field-emission scanning electron microscopy, energy-dispersive spectroscopy, and x-ray photoelectron spectroscopy techniques. The sensor has been packaged using thick-film technology and encapsulated by a dam-and-fill approach. The packaged device has been tested in various pH buffer solutions, and a sensitivity of nearly 42.1 mV/pH has been achieved. A simulation program with integrated circuit emphasis (SPICE) macromodel of the Al2O3-gate ISFET is empirically derived from the experimental results, and the extracted electrochemical parameters have been reported. The drift and hysteresis characteristics of the Al2O3-gate ISFET were also studied, and the obtained drift rates for different pH buffer solutions of 4, 7, and 10 are 0.136 μA/min, 0.124 μA/min, and 0.108 μA/min, respectively. A hysteresis of nearly 5.806 μA has been obtained. The developed sensor has high sensitivity along with low drift and hysteresis.

Characterization of dynamics and information processing of integrate-and-fire neuron models

The integrate-and-fire (IF) model is the most widely used simple spiking neuron model in neuromorphic computing as well as in artificial neural network algorithms. Here, we characterize the dynamics and information processing of IF models using computer simulations and information-theoretic approaches. Neural dynamics is analysed by means of the time evolution of axonal spikes and the phase-plane portrait, and the coding efficiency of a neuron is estimated by the ratio of mutual information of input and output spikes for the binary hidden neural state. The exponential IF model exhibits higher similarity to the biophysical model in both neural dynamics and coding, compared to other IF type models. Electronic circuit simulations based on the simulation programme with integrated circuit emphasis reveal the nonlinear current–voltage characteristics of the IF neuron models and criticalities in the neural networks. Relevant information-theoretic measures indicate that the computational capabilities of neuromorphic devices largely depend on the neuron models. Such an approach combined with the analysis of neural dynamics provides a useful tool to investigate underlying dynamics of mathematical neuron models; it is applicable to the design and evaluation of neuromorphic models.

An artificial neural network chip based on two-dimensional semiconductor

Recently, research on two-dimensional (2D) semiconductors has begun to translate from the fundamental investigation into rudimentary functional circuits. In this work, we unveil the first functional MoS2 artificial neural network (ANN) chip, including multiply-and-accumulate (MAC), memory and activation function circuits. Such MoS2 ANN chip is realized through fabricating 818 field-effect transistors (FETs) on a wafer-scale and high-homogeneity MoS2 film, with a gate-last process to realize top gate structured FETs. A 62-level simulation program with integrated circuit emphasis (SPICE) model is utilized to design and optimize our analog ANN circuits. To demonstrate a practical application, a tactile digit sensing recognition was demonstrated based on our ANN circuits. After training, the digit recognition rate exceeds 97%. Our work not only demonstrates the protentional of 2D semiconductors in wafer-scale integrated circuits, but also paves the way for its future application in AI computation.

Modulation Performance Enhancement of Directly Modulated Injection-Locked Semiconductor Lasers Using an Equivalent Electrical Circuit

We propose an equivalent electrical circuit model to evaluate the direct modulation performance of optically injection-locked (OIL) semiconductor lasers. We modeled the equivalent circuit of the OIL laser based on alternating complex envelope representations, simulated it using the Simulation Program with Integrated Circuit Emphasis (SPICE), and analyzed the frequency response of the OIL laser. Although the frequency response of the OIL laser is better than that of a free-running laser, its 3-dB modulation performance is degraded by the relaxation oscillation that occurs during direct modulation of the semiconductor laser. To overcome this limitation and maintain the maximum modulation performance within the entire locking range, we also designed an electrical filter to preprocess the electrical modulation signal and compensate for the non-flat modulation output of the OIL laser. The damping ratio of the directly modulated OIL laser increased by 0.101 (280%) and its settling time decreased by >0.037 (44%) when the electrical compensation circuit was added, exhibiting a flat 3-dB modulation bandwidth of 28.79 GHz.

Statistical Learning of IC Models for System-Level ESD Simulation

To enable accurate system-level electrostatic discharge (ESD) simulation, this article applies statistical learning to obtain I/O port models of the victim integrated circuits (ICs). A quasi-static <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I–V</i> model derived using kernel regression can capture the circuit board dependency of the behavior observed at the I/O pin, regardless if there is snapback. The non-parametric kernel model can be reduced to a system-specific parametric model, which has smaller requirements for computing time and memory. In some cases, transient system-level ESD simulation may require the IC model to replicate the dynamic behavior of the nonlinear circuit. A recurrent neural network is demonstrated to be a suitable model in such cases. This article provides a detailed RNN training flow for IC pin modeling, and presents a Verilog-A implementation of the RNN for use with Simulation Program with Integrated Circuit Emphasis (SPICE)-type simulators.

A High-Speed Bipolar Hybrid Cockcroft–Walton/Dickson Multiplier for Shockwave Non-thermal Food Processing

For the design of shockwave non-thermal food processing systems, a novel high-speed bipolar voltage multiplier is presented in this paper. Unlike conventional high voltage multipliers, the proposed voltage multiplier has bipolar topology employing hybrid Cockcroft-Walton/Dickson multipliers (HCWDMs), where the bipolar HCWDM is driven by a driver circuit generating high speed rectangular pulses. Therefore, the proposed multiplier can achieve high speed operation. Through simulation program with integrated circuit emphasis (SPICE) simulations and experiments, the validity of the proposed multiplier is confirmed. The SPICE simulations and experiments reveal that the proposed multiplier outperforms the conventional HCWDM.

Predicting Early EVA Degradation in Photovoltaic Modules From Short Circuit Current Measurements

One of the common failures in photovoltaic modules is the degradation of the ethylene-vinyl acetate (EVA) encapsulant due to prolonged ultraviolet exposure and other environmental stress factors, such as temperature and humidity. Experimental studies have shown that significant reduction in the optical transmission due to EVA degradation leads to loss in the available power by more than 50%. In this article, a novel approach to predict the early degradation of EVA encapsulant is proposed by correlating EVA degradation with short-circuit current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SC</sub> ). An electrical circuit simulator, simulation program with integrated circuit emphasis (SPICE), is used to evaluate the short-circuit current obtained under varying optical transmission caused by EVA discoloration. The simulation follows three steps: simulation of the transmitted solar spectrum; simulation of the spectral short-circuit current density; and simulation of the current-voltage (I-V) curve to obtain short-circuit current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SC</sub> ), maximum power output (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> ), open-circuit voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OC</sub> ) and fill factor. Results show that the reduction in short-circuit current due to EVA degradation differs from the reductions expected due to a spectrally-uniform reduction of intensity of the solar irradiance. Both types of variation are linear, however, the slope due to EVA degradation is larger than the slope obtained for normal intensity variations in the solar irradiance. This model, when applied in conjunction with solar irradiance measurements, can predict early onset of EVA encapsulant failure, thereby enabling preventative measures to be taken.

Exponential Matrix–Rational Approximation (EM-RA) Model for SWCNT Bundle and Hybrid Cu-CNT Interconnects

This article presents a variation-aware exponential matrix–rational approximation (EM-RA) model for the signal integrity analysis in single-walled carbon nanotube (SWCNT) bundle and hybrid copper-CNT (Cu-CNT) on-chip interconnects. The variations include temperature (300–500 K) only, and temperature (300–500 K) and dielectric surface roughness (10–180 pm) both. The transient analysis is carried out for the signal integrity parameters, crosstalk and propagation delay, estimation using the proposed EM-RA model. The results obtained using the proposed model are compared with the industry-level simulation program with an integrated circuit emphasis (SPICE) simulator. The comparison shows excellent agreement for the results with less than 1% error. The proposed model is also compared for the computational time complexity. It is observed that a speed-up factor of 74.24 and 48.35 is attained using the proposed temperature-parameterized model during the analysis of coupled-two and coupled-three interconnect lines, respectively. The speed-up further increases to 485.41 and 378.35 for coupled-two and coupled-three lines, respectively, when the temperature and dielectric surface roughness parametrized EM-RA model is used. This computational CPU time expense efficiency and the accuracy of the proposed model in comparison to the HSPICE simulator ensures immense possibility regarding its implementation in computer-aided design (CAD) tools for carrying out the transient analysis of SWCNT bundle and Cu-CNT interconnect lines. Encouraging results for the eye-diagram analysis reports 95.54% and 99.37% of the eye height and eye width for the SWCNT network, and 99.77% and 99.96% of the eye height and eye width for the Cu-CNT.

Modeling and Simulation of Monolithic Single-Supply Power Operational Amplifiers

In this paper a simple PSpice (Personal Simulation Program with Integrated Circuit Emphasis) macro-model was developed, and verified for monolithic power operational amplifiers operated with a single-supply voltage. The proposed macro-model is developed using simplification and build-up techniques for macro-modeling of operational amplifiers and simulates the basic static and dynamic characteristics, including input impedance, small-signal frequency responses at various voltage gains, output power versus supply voltage, slew-rate-limiting, voltage limiting, output offset voltage versus supply voltage ripples, and output resistance. Furthermore, the macro-model also takes into account the ground reference voltage in the amplifier at a single power supply voltage. The model is implemented as a hierarchical structure suitable for the PSpice circuit simulation platform. The sub-circuit is built using standard PSpice components and analog behavioral modeling blocks. The accuracy of the model is verified by extracting the model parameters for single-supply power operational amplifier TDA2005 from ST Microelectronics as example. The effectiveness of the model is validated by comparing the simulation results of the electrical parameters with the corresponding measured values obtained by experimental testing of sample circuits. The comparative analysis shows that the relative error of the modeled large-signal parameters is less than 15%. Moreover, an error of 15% is quite acceptable, considering the technological tolerances of the electrical parameters for this type of analog ICs.

Edge scattering limited crosstalk analysis in adjacent multilayer graphene interconnects and its impact on gate oxide reliability

PurposeThis paper aims to present the edge scattering dominant circuit modeling. The effect of crosstalk on gate oxide reliability (GOR), along with the mitigation using shielding technique is further studied.Design/methodology/approachAn equivalent distributed Resistance Inductance Capacitance circuit of capacitively coupled interconnects of multilayer graphene nanoribbon (MLGNR) has been considered for T Simulation Program with Integrated Circuit Emphasis (TSPICE) simulations under functional and dynamic switching conditions. Complementary metal oxide semiconductor driver transistors are modeled by high performance predictive technology model that drive the distributed segment with a capacitive load of 0.001 fF, VDD and clock frequency as 0.7 V and 0.2 GHz, respectively, at 14 nm technology node.FindingsThe results reveal that the crosstalk induced delay and noise area are dominated by the overall mean free path (MFP) (i.e. including the effect of edge roughness induced scattering), in contrary to, acoustic and optical scattering limited MFP with the temperature, width and length variations. Further, GOR, estimated in terms of average failure rate (AFR), shows that the shielding technique is an effective method to minimize the relative GOR failure rate by, 0.93e-7 and 0.7e-7, in comparison to the non-shielded case with variations in interconnect’s length and width, respectively.Originality/valueConsidering realistic circuit modeling for MLGNR interconnects by incorporating the edge roughness induced scattering mechanism, the outcomes exhibit more penalty in terms of crosstalk induced noise area and delay. The shielding technique is found to be an effective mitigating technique for minimizing AFR in coupled MLGNR interconnects.

A Unified and Open LTSPICE Memristor Model Library

In this paper, a unified and open linear technology simulation program with integrated circuit emphasis (LTSPICE) memristor library is proposed. It is suitable for the analysis, design, and comparison of the basic memristors and memristor-based circuits. The library could be freely used and expanded with new LTSPICE memristor models. The main existing standard memristor models and several enhanced and modified models based on transition metal oxides such as titanium dioxide, hafnium dioxide, and tantalum oxide are included in the library. LTSPICE is one of the best software for analysis and design of electronic schemes. It is an easy to use, widespread, and free product with very good convergence. Memristors have been under intensive analysis in recent years due to their nano-dimensions, low power consumption, high switching speed, and good compatibility with traditional complementary metal oxide semiconductor (CMOS) technology. In this work, their behavior and potential applications in artificial neural networks, reconfigurable schemes, and memory crossbars are investigated using the considered memristor models in the proposed LTSPICE library. Furthermore, a detailed comparison of the presented LTSPICE memristor model library is conducted and related to specific criteria, such as switching speed, operating frequencies, nonlinear ionic drift representation, boundary effects, switching modes, and others.

Modeling of Bias-Dependent Effective Velocity and Its Impact on Saturation Transconductance in AlGaN/GaN HEMTs

In this article, we present a surface-potential-based approach to model the bias-dependent effective velocity observed in AlGaN/GaN high-electron-mobility transistors (HEMTs) due to optical phonon scattering. Our model precisely reproduces the progressive decrease in the saturation velocity in GaN HEMTs with increasing gate voltages, as reported in the literature, which is predominantly due to the scattering of electrons, forming the high-density two-dimensional electron gas (2DEG), by optical phonons at high overdrive voltages. We show that this dependence differs from the traditional mobility degradation models in terms of its impact on the device current-voltage (I- V) characteristics and illustrate how the inclusion of a velocity saturation model also provides the model users with an additional handle for parameter extraction. The model is explicit and, by virtue of its Simulation Program with Integrated Circuit Emphasis (SPICE) compatibility, is readily implemented in the industry-standard Advanced SPICE Model for HEMTs (ASM-HEMTs) model and has been validated against experimental dc I-V and RF S-parameter measurements of an in-house GaN device.

Custom measurement system for memristor characterisation

A cheap, compact and customisable characterisation system for memristor devices, working between ± 10 V, is presented. SPICE (Simulation Program with Integrated Circuit Emphasis) simulations are performed to verify the circuit feasibility and a proper software is developed to drive the system. The potentiality of the realised system is tested by performing several electrical measurements on both Cu/HfO2/Pt memristors and two-terminals commercial devices.