Integer Motion Estimation Research Articles

Algorithmic and architectural co-design for integer motion estimation of AVS

The video part of A VS has been finalized, in order to enhance coding performance. AVS video standard adopts some new features for motion estimation, such as variable block size search, multiple reference frames, and motion vector prediction. However, the better performance comes at the price of high computational complexity, data dependence and memory access requirement. These new features also make the hardware implementation more difficult, especially for real-time applications. In this paper, we firstly propose an integer motion estimation algorithm from hardware-oriented viewpoint. Experimental results show that the proposed algorithm has almost the same performance as the reference software of AVS in SDTV applications. Then the corresponding VLSI architecture is presented. The VLSI architecture has been described in Verilog HDL and synthesized using 0.18 mum Artisan CMOS cells library. The circuit totally costs about 400 K equivalent logic gates. At 108 MHz working frequency, the circuit can meet the real-time requirement for SDTV (720times576, 25 fps) applications, with the search area of 192times192. The co-design obtains better tradeoff between performance and gate-count

Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder

H.264/AVC significantly outperforms previous video coding standards with many new coding tools. However, the better performance comes at the price of the extraordinarily huge computational complexity and memory access requirement, which makes it difficult to design a hardwired encoder for real-time applications. In addition, due to the complex, sequential, and highly data-dependent characteristics of the essential algorithms in H.264/AVC, both the pipelining and the parallel processing techniques are constrained to be employed. The hardware utilization and throughput are also decreased because of the block/MB/frame-level reconstruction loops. In this paper, we describe our techniques to design the H.264/AVC video encoder for HDTV applications. On the system design level, in consideration of the characteristics of the key components and the reconstruction loops, the four-stage macroblock pipelined system architecture is first proposed with an efficient scheduling and memory hierarchy. On the module design level, the design considerations of the significant modules are addressed followed by the hardware architectures, including low-bandwidth integer motion estimation, parallel fractional motion estimation, reconfigurable intrapredictor generator, dual-buffer block-pipelined entropy coder, and deblocking filter. With these techniques, the prototype chip of the efficient H.264/AVC encoder is implemented with 922.8 K logic gates and 34.72-KB SRAM at 108-MHz operation frequency.

Analysis and architecture design of variable block-size motion estimation for H.264/AVC

Variable block-size motion estimation (VBSME) has become an important video coding technique, but it increases the difficulty of hardware design. In this paper, we use inter-/intra-level classification and various data flows to analyze the impact of supporting VBSME in different hardware architectures. Furthermore, we propose two hardware architectures that can support traditional fixed block-size motion estimation as well as VBSME with less chip area overhead compared to previous approaches. By broadcasting reference pixel rows and propagating partial sums of absolute differences (SADs), the first design has the fewer reference pixel registers and a shorter critical path. The second design utilizes a two-dimensional distortion array and one adder tree with the reference buffer that can maximize the data reuse between successive searching candidates. The first design is suitable for low resolution or a small search range, and the second design has advantages of supporting a high degree of parallelism and VBSME. Finally, we propose an eight-parallel SAD tree with a shared reference buffer for H.264/AVC integer motion estimation (IME). Its processing ability is eight times of the single SAD tree, but the reference buffer size is only doubled. Moreover, the most critical issue of H.264 IME, which is huge memory bandwidth, is overcome. We are able to save 99.9% off-chip memory bandwidth and 99.22% on-chip memory bandwidth. We demonstrate a 720-p, 30-fps solution at 108 MHz with 330.2k gate count and 208k bits on-chip memory.

Fast integer-pel and fractional-pel motion estimation for H.264/AVC

This paper gives out a fast motion estimation algorithm for H.264/AVC, which has almost the same quality performance as that of the Full Search scheme and also provides a strategy to balance the quality performance and the search speed. Integer-pel search is the most time consuming module for motion estimation. In this paper a hybrid Unsymmetrical-cross Multi-hexagon-grid Search (UMHexagonS) algorithm is introduced, which well solves the false motion vector estimation problem because of the local-minimum. As results, it saves more than 90% on search time whereas the averaging PSNR loss is less than 0.056 dB for all tested sequences with different motion extent compared with the Fast Full Search scheme. Fractional-pel fast search is not negligible when the integer motion estimation has been extensively speeded up. By utilizing the property of uni-modal error surface inside the fractional-pel search window, a novel Center Biased Fractional-pel Search (CBFPS) algorithm is proposed in this paper, which can save 30–50% computation compared with the Full Fractional-pel Search scheme. Early termination is another problem discussed in this paper, to construct a complete motion estimation method, giving a uniform method which can cover a wide range of applications, terminating the program at early and right stage is certainly required. A model based on the Normative SAD Difference (NSD) is given to assist the termination decision-making, and a tradeoff between the search speed and the reconstructed quality can be achieved by changing a modulation factor.