Instruction Set Simulator Research Articles

Adaptive simulation with Virtual Prototypes in an open-source RISC-V evaluation platform

Abstract Recently, Virtual Prototypes (VPs) were introduced for the emerging RISC-V Instruction Set Architecture (ISA) and become an important part of the growing RISC-V ecosystem. A central component of the VP is the Instruction Set Simulator (ISS). VPs should provide a high simulation performance and at the same time yield accurate results, which are two conflicting requirements. To tackle this problem, we present an efficient VP-based adaptive simulation that is tailored for the RISC-V ISA and allows to seamlessly switch the accuracy setting in the ISS at runtime. This enables to selectively simulate the application as fast as possible and as accurate as necessary. In this paper we focus on the performance impact of different accuracy settings and leave the evaluation of accuracy results for future work. Our RISC-V experiments, using bare-metal and operating system based benchmarks, demonstrate that up-to 543x speed-up is possible with a JIT-based setting in the ISS.

On-Demand Remote Software Code Execution Unit Using On-Chip Flash Memory Cloudification for IoT Environment Acceleration

In an Internet of Things (IoT)-configured system, each device executes on-chip software. Recent IoT devices require fast execution time of complex services, such as analyzing a large amount of data, while maintaining low-power computation. As service complexity increases, the service requires high-performance computing and more space for embedded space. However, the low performance of IoT edge devices and their small memory size can hinder the complex and diverse operations of IoT services. In this paper, we propose a remote on-demand software code execution unit using the cloudification of on-chip code memory to accelerate the program execution of an IoT edge device with a low-performance processor. We propose a simulation approach to distribute remote code executed on the server side and on the edge side according to the program’s computational and communicational needs. Our on-demand remote code execution unit simulation platform, which includes an instruction set simulator based on 16-bit ARM Thumb instruction set architecture, successfully emulates the architectural behavior of on-chip flash memory, enabling embedded devices to accelerate and execute software using remote execution code in the IoT environment.

RISC-V3: A RISC-V Compatible CPU With a Data Path Based on Redundant Number Systems

Redundant number systems (RNS) are a well-known technique to speed up arithmetic circuits. However, in a complete CPU, arithmetic circuits using RNS were only included on subcircuit level e.g. inside the Arithmetic Logic Unit (ALU) for realization of the division. Still, extending this approach to create a CPU with a complete data path based on RNS can be beneficial for speeding up data processing, due to avoiding conversions in the ALU between RNS and binary number representations. Therefore, with this paper we present a new CPU architecture called RISC-V3 which is compatible to the RISC-V instruction set, but uses an RNS number representation internally to speed up instruction execution times and therefore increase the system performance. RISC-V is very suitable for RNS because it does not have a flags register which is expensive to calculate when using an RNS. To present reliable performance numbers, arithmetic circuits using RNS were realized in different semiconductor technologies. Moreover, an instruction set simulator was used to estimate system performance for a benchmark suite (Embench). Our results show, that we are up to 81% faster with the RISC-V3 architecture compared to a binary one, depending on the executed benchmark and CMOS technology.

HdSC: A Fast and Preemptive Modeling for on Host HdS Development

In modern embedded systems, the Hardware-dependent Software (HdS) plays a critical role due to its processor and platform dependency, such as device drivers and boot initialization. To support HdS development starting in an initial system design phase, fast and accurate preemptive processor models should be provided for simulating the software. These models should provide a register level interface to enable a compatible programming view on the host machine environment. This paper presents a strategy for processor modeling that enables HdS development, using the host machine tool chain. The proposed approach supports the specification of platform components, such as processor, software and devices accessed through the data bus and interruption interfaces. An adaptive technique for timing estimation is being proposed, which is very accurate and show a high simulation performance. Supporting the device driver development and interruption service routines, these two features can be implemented and simulated at an early system design phase and requiring no Instruction Set Simulator (ISS). This ISS model would be required only for performance and accuracy comparison purposes. Experimental results show that the virtual platform specified using this proposed approach can perform faster (up to 760x speed up) and high accurate (up to 12%) software simulation on native host environment.

RISC-V based virtual prototype: An extensible and configurable platform for the system-level

Abstract Internet-of-Things (IoT) opens a new world of possibilities for both personal and industrial applications. At the heart of an IoT device, the processor is the core component. Hence, as an open and free instruction set architecture RISC-V is gaining huge popularity for IoT. A large ecosystem is available around RISC-V, including various RTL implementations at one end and high-speed instruction set simulators (ISSs) at the other end. These ISSs facilitate functional verification of RTL implementations as well as early SW development to some extent. However, being designed predominantly for speed, they can hardly be extended to support further system-level use cases such as design space exploration, power/timing/performance validation or analysis of complex HW/SW interactions. In this paper, we propose and implement a RISC-V based Virtual Prototype (VP) with the goal of filling this gap. We provide a 32 and 64 bit RISC-V core supporting the IMAC instruction set with different privilege levels, the RISC-V CLINT and PLIC interrupt controllers and an essential set of peripherals. We support simulation of (mixed 32 and 64 bit) multi-core platforms, provide SW debug and coverage measurement capabilities and support the FreeRTOS and Zephyr operating systems. The VP is designed as extensible and configurable platform with a generic bus system and implemented in standard-compliant SystemC and TLM-2.0. The latter point is very important, since it allows to leverage cutting-edge SystemC-based modeling techniques needed for the mentioned use cases. Our VP allows a significantly faster simulation compared to RTL, while being more accurate than existing ISSs. Finally, our RISC-V VP is fully open source (MIT licence) to help expanding the RISC-V ecosystem and stimulating further research and development.

An Exploration of Approaches to Instruction Pipeline Implementation for Cycle-Accurate Simulators of «Elbrus»

Software simulation is of a big importance during development of processors as they provide access to hardware under development. Cycle-accurate simulators allow software engineers to design and optimize high-performance algorithms and programs with considerations of features and characteristics of processors being in development. This is especially important for architectures, whose performance is mainly achieved by advanced compiler optimizations. One of the core aspects of a cycle-accurate simulator is the way it simulates the pipeline of the target processor. A pipeline model has high impact on an overall structure of a simulator and its potential performance and accuracy. The main goal of this paper is to develop and analyze different approaches to pipeline simulation of “Elbrus” microprocessors, which let us reuse functionality of existing instruction set simulator and achieve good balance of performance and accuracy. We briefly describe features of “Elbrus” microprocessors and specifics of existing instruction set simulator, relevant for cycle-accurate simulation. We make several simple, but general and useful observations about various aspects of pipeline behavior in context of accurate and efficient cycle-accurate simulation of microprocessors. These observations are then used as a basis for justification, development and analysis of the several approaches to the pipeline simulation, described in this paper. We describe four different approaches, starting from simple and obvious one, which is then successively transformed into more advanced ones through several iterations. We analyze limitations of proposed approaches and outline further work.

Smashing OpenFlow's “atomic” actions: Programmable data plane packet manipulation in hardware

SummaryRecently, with new hardware architectures such as Reconfigurable Match Tables and languages such as P4, the Software Defined Networking community has started to bring line‐rate data plane programmability inside switching chipsets. Starting from the original OpenFlow's match/action abstraction, most of the work has so far focused on key improvements in matching flexibility. Conversely, the “action part,” ie, the set of operations (such as encapsulation or header manipulation) performed on packets after the forwarding decision, has received way less attention. Goal of this paper is to move beyond the idea of “atomic,” preimplemented, actions, and rather make them programmable while retaining high speed multi‐Gbps operation. To this purpose, we propose a domain‐specific HW architecture, called Packet Manipulation Processor (PMP), able to efficiently implement such actions. Both a PMP C++ instruction set simulator and a NetFPGA prototype have been developed. The performances of the PMP have been verified with three nontrivial use cases (tunneling, NAT, and ARP reply generation), showing that also in the worst case the throughput is well above 10 Gbps.

Energy efficient configuration unification and compression for CGRAs

Energy efficiency has become one the most important factors in today's processing platforms. Coarse-grained reconfigurable architectures (CGRAs) have turned out to perform well in this area. In this paper, we have proposed two methods to enhance their energy efficiency. The first method decreases the power consumption of a CGRA by reducing the number of occurring transitions of the context switching process. The second one decreases the energy consumption of a CGRA through volume shrinkage of its context memory. Our results show up to 83% of the context memory energy can be reduced by using our proposed method. In addition, a high level instruction-set simulator for CGRA has been presented in this paper.

Testing distributed embedded systems through logic analyzer

Testing distributed embedded systems is complex as the individual systems connected on to the network are heterogeneous in nature.The communication system that is used for establishing the networking also varies greatly leading to different testing requirements. Testing of embedded systems can be carried using different methods that include Scaffolding, assert macros, instruction set simulators. In-circuit emulators, logic analyzers each requiring establishment of different testing environment required for undertaking actual testing. Testing of any embedded systems involves testing hardware, testing hardware dependent code, and testing hardware independent code. Logic analyzers are generally used for testing proper working of the Hardware.In this paper, a framework is presented using which testing of hardware distributed across the distributed embedded system using logic analyzer is presented.

Loop aware CFG matching strategy for accurate performance estimation in IR-level native simulation

Native simulation is a promising virtual prototyping candidate to accelerate design space exploration of hardware/software systems, early software developments and functional verification. However, it originally fails to provide non-functional information needed for software performance estimation. To add this capability, the general approach is to extract performance metrics from target binary code and back-annotate it in the high-level code from which the binary was generated. However, due to compiler optimizations, the high-level code and the binary code usually have different structures which makes software annotation a complex task. This work proposes a loop-based mapping scheme that reflects optimizations from the binary to the high-level IR for the purpose of precisely placing performance annotations in the software and yielding accurate performance estimates. Experiments on instruction count show in average around 2% of error while conserving a considerable speedup compared to instruction set simulation.

UVM-powered hardware/software co-verification

In traditional verification environment, hardware and software involve isolated design and verification. Due to the demise of Moore's law, the processor's frequency is no longer increasing. This demise of Moore's law and time-to-market pressures drive the wave of new technology where hardware and software are tightly integrated. This is done in order to increase the speed of computation. Moreover, in domains like Data Analytics, data has to be processed in real time and that too at low latency. Solarflare's Application On-load Engine (AOE) represents a platform where an FPGA processing engine integrates with a low latency server for applications that require real time and low latency of data processing. This is where co-verification provides a solution for integration of hardware and software. Universal Verification Methodology (UVM) doesn't support co-verification and uses Direct Programming Interface (DPI) for co-simulation. Vlang, which is built on the top of D, a systems programming language, has complete implementation of UVM version 1.2. In co-verification, emulation of software is run along with the hardware verification where, software is emulated separately on Instruction Set Simulator (ISS).

HybridVerifier: A Cross-Platform Verification Framework for Instruction Set Simulators

Instruction set simulators (ISSs) play a critical role in the design cycle of embedded systems. However, as ISSs evolve and increase in complexity, not only new bugs might be introduced but also old latent bugs might be revealed. Finding these bugs based on the simulator output might be a challenging task. This letter presents HybridVerifier, a novel and retargetable framework for ISS verification. It relies on hybrid simulation between the ISS and the host processor (x86), using the host’s memory as a reference for the simulated architecture. We demonstrate the effectiveness of our approach in three different scenarios: 1) ISS model verification; 2) processor specific libraries/functionalities; and 3) cross compiler bugs.

Application specific instruction set processor for sensor conditioning in automotive applications

In the automotive electronic market, sensor conditioning is one of the driving applications. Sensor solutions are pervasive in the vehicle, while signal processing in such application is getting more and more complex. Currently the design strategy is often the standard ASIC flow, but the design effort can be reduced by automatic or platform-aided design strategies, or by using software-based solutions. In this paper SensASIP platform is presented. It is a design platform targeting a microprocessor architecture enhanced by dedicated instructions for computing intensive sensor signal processing tasks. SensASIP allows a seamless design flow from MATLAB-based algorithm definition and instruction set design and simulation, down to hardware macrocell HDL description and implementation in CMOS technology. SensASIP features are described through two automotive sensor conditioning examples. Special focus is put on its increased flexibility and reduced design-effort vs. standard ASIC design approach and on its low complexity overhead vs. other state-of-art software-based solutions.

Efficient asynchronous interrupt handling in a full-system instruction set simulator

Instruction set simulators (ISS) have many uses in embedded software and hardware development and are typically based on dynamic binary translation (DBT), where frequently executed regions of guest instructions are compiled into host instructions using a just-in-time (JIT) compiler. Full-system simulation, which necessitates handling of asynchronous interrupts from e.g. timers and I/O devices, complicates matters as control flow is interrupted unpredictably and diverted from the current region of code. In this paper we present a novel scheme for handling of asynchronous interrupts, which integrates seamlessly into a region-based dynamic binary translator. We first show that our scheme is correct, i.e. interrupt handling is not deferred indefinitely, even in the presence of code regions comprising control flow loops. We demonstrate that our new interrupt handling scheme is efficient as we minimise the number of inserted checks. Interrupt handlers are also presented to the JIT compiler and compiled to native code, further enhancing the performance of our system. We have evaluated our scheme in an ARM simulator using a region-based JIT compilation strategy. We demonstrate that our solution reduces the number of dynamic interrupt checks by 73%, reduces interrupt service latency by 26% and improves throughput of an I/O bound workload by 7%, over traditional per-block schemes.

Highly Efficient and Effective Approach for Synchronization-Function-Level Parallel Multicore Instruction-Set Simulations

Multicore instruction-set simulation (MCISS) has become more and more important due to tremendous increase in number of multicore designs. To boost the speed of MCISS, one of the most effective and commonly used approaches is parallel simulation. However, timing synchronization must be applied to ensure accurate simulation results of parallel MCISS, and may induce huge synchronization overhead. In this paper, we propose a highly efficient and effective parallel MCISS approach by synchronizing timing before each synchronization function (SF) call. We improve the applicability of the state-of-the-art critical-section-level simulation approach with a generic blocking/nonblocking send/receive model covering all types of SFs. To further reduce synchronization overhead, we also introduce optimization methods such as a hybrid scheduling technique and provide an analysis algorithm that helps the designers to choose the host platform with the best simulation performance. Experiments show that the proposed approach attains a simulation speed of up to 285 MIPS, while producing accurate timing and functional results.

Energy Modeling of Software for a Hardware Multithreaded Embedded Microprocessor

This article examines a hardware multithreaded microprocessor and discusses the impact such an architecture has on existing software energy modeling techniques. A framework is constructed for analyzing the energy behavior of the XMOS XS1-L multithreaded processor and a variation on existing software energy models is proposed, based on analysis of collected energy data. It is shown that by combining execution statistics with sufficient data on the processor’s thread activity and instruction execution costs, a multithreaded software energy model used with Instruction Set Simulation can yield an average error margin of less than 7%.

Function-level profiling for embedded software with QEMU

Function-level profiling is crucial for optimised embedded software which has severe constraints on hardware resources, low power consumption, real-time responses, and so on. In this work, we provide a fast and reliable solution by utilising an instruction set simulator named QEMU and creating an analyser tool. We developed a tracing module inside the simulator to trace execution information of software at run-time and record it in a log file. Our implementation takes advantage of the dynamic binary translation of QEMU to keep its speed fast and use an analyser tool to analyse the log file and create a function-level profile. We implemented our solution methodology for the ARM architecture, and evaluated it with various kinds of embedded applications.

Achieving spilling-friendly register file assignment for highly distributed register files

Distributed register file architectures divide registers into multiple sets, and it follows that the register files could be small. This can increase the frequency of spilling if register allocation encounters high register pressure, which will reduce the performance. That is, there is extra spilling to handle the pressure and results in performance decline. One of the factors that can produce high pressure is improper register file assignment. Register file assignment is a phase that assigns virtual registers to suitable register files and avoids communication costs. To reduce spilling in the phase of register file assignment, this paper proposes the SPIlling-FRiendly (SPIFR) method, which attempts to improve spilling by estimating the spilling cost from two aspects: assignment and spilling. We used MiBench and EEMBC benchmarks in experiments performed with the Open64-based compiler and a cycle-accurate instruction set simulator. The MiBench experimental results show that the SPIFR method improved the average cycle counts of the benchmarks by 6.0 %. For the kernels of the benchmarks, the method improved the average cycle counts by 20.5 % and reduced the average spilling ratio by 19.0 %. The results on the EEMBC benchmarks indicate that the method improved the cycle counts with the average speedup of 7.0 %, the speedup average of the kernel functions was 11.3 %, and the average reduction in the spilling ratio was 11.7 %, respectively. We conclude that the SPIFR method can reduce spilling and increase the performance.

Dominant Block Guided Optimal Cache Size Estimation to Maximize IPC of Embedded Software

Embedded system software is highly constrained from performance, memory footprint, energy consumption and implementing cost view point. It is always desirable to obtain better Instructions per Cycle. Instruction cache has major contribution in improving IPC. Cache memories are realized on the same chip where the processor is running. This considerably increases the system cost as well. Hence, it is required to maintain a trade off between cache sizes and performance improvement offered. Determining the number of cache lines and size of cache line are important parameters for cache designing. The design space for cache is quite large. It is time taking to execute the given application with different cache sizes on an instruction set simulator to figure out the optimal cache size. In this paper, a technique is proposed to identify a number of cache lines and cache line size for the L1 instruction cache that will offer best or nearly best IPC. Cache size is derived, at a higher abstraction level, from basic block analysis in the Low Level Virtual Machine environment. The cache size estimated is cross validated by simulating the set of benchmark applications with different cache sizes in simple scalar simulator. The proposed method seems to be superior in terms of estimation accuracy and estimation time as compared to the existing methods for estimation of optimal cache size parameters like cache line size, number of cache lines.

SystemC fine-grained HW–SW fully heterogeneous WSN simulation and UML metamodel behavioural extraction

Wireless sensor networks are becoming an essential part of our lives, being frequently used for monitoring and control applications. It is essential that these networks be modelled before their deployment so as to identify the possible problems that may arise. SystemC is fast becoming an important modelling paradigm in the context of SoC design and verification, as well as other fields that require accurate (sometimes Transaction Level Modelled) characterization of digital processes (i.e.: communication on a bus interface, over a radio channel, etc). SystemC has successfully been used in the IDEA1 WSN exploration framework to model wireless sensor networks at the timed functional level of abstraction. As a first contribution, we refined the initial implementation of IDEA1 to cope with a finer-grade simulation of the node hardware, going beyond the timed functional description of the node and enabling support for a bus cycle-accurate simulation. The new and improved version is called IDEA1TLM and can also model the software aspect of the nodes in question by means of a custom-built instruction set simulator called BLISS. The second part of this contribution focuses on extracting the metamodel from SystemC source files. The metamodel is the information which can be generated concerning the model; in our case, a diagram representation with states and transitions between them. Because current work focuses on generating C++ code (SystemC-compliant) from UML metamodels, there is no support to achieve this in reverse. We developed a tool called DiaSig that takes SystemC source files as input and generates UML diagrams of the model in SVG format.