Instruction Set Simulator Research Articles

An interactive codesign environment for domain-specific coprocessors

Energy-efficient embedded systems rely on domain-specific coprocessors for dedicated tasks such as baseband processing, video coding, or encryption. We present a language and design environment called GEZEL that can be used for the design, verification and implementation of such coprocessor-based systems.The GEZEL environment creates a platform simulator by combining a hardware simulation kernel with one or more instruction-set simulators. The hardware part of the platform is programmed in GEZEL, a deterministic, cycle-true and implementation-oriented hardware description language. GEZEL designs are scripted, allowing the hardware configuration of the platform simulator to be changed quickly without going through lengthy recompiles. For this reason, we call the environment interactive. We present the execution ladder as an optimization framework to balance interactivity against simulation speed.We demonstrate our approach using several designs including an AES encryption coprocessor and a Viterbi decoding coprocessor. We discuss the advantages of our approach as opposed to more conventional approaches using SystemC and Verilog/VHDL.

A Simulation and Exploration Technology for Multimedia-Application-Driven Architectures

The increasing of computational power requirements for DSP and Multimedia application and the needs of easy-to-program development environment has driven recent programmable devices toward Very Long Instruction Word (VLIW) [1] architectures and Hw-Sw co-design environments [2]. VLIW architecture allows generating optimized machine code from high-level languages exploiting Instruction Level Parallelism (ILP) [3]. Furthermore, applications requirements and time to market constraints are growing dramatically moving functionalities toward System on Chip (SoC) direction. This paper presents VLIW-SIM, an Application-Driven Architecture-design approach based on Instruction Set simulation. VLIW architectures and Instruction Set simulation were chosen to fulfill multimedia domain requirements and to implement an efficient Hw-Sw co-design environment. The VLIW-SIM simulation technology is based on pipeline status modeling, Simulation cache and Simulation Oriented Hw description. An effective support for Hw-Sw co-design requires high simulation performance (in terms of Simulated Instruction per Second--SIPS), flexibility (the ability to represent a number of different architectures) and cycle accuracy. There is a strong trade-off between these features: cycle accurate or close to cycle accurate simulation have usually low performance [4, 5]. Good simulation performance can be obtained loosing the simulator flexibility. Moreover SoC simulation requires a further degree of flexibility in simulating different components (core, co-processors, memories, buses). The proposed approach is focused on interpretative (not compiled [6]) re-configurable Instruction Set Simulator (ISS) in order to support both application design and architecture exploration. VLIW-SIM main features are: efficient host resource allocation, Instruction Set and Architecture description Flexibility (Instruction Set Dynamic Generation and Simulation Oriented Hardware Description), Step by step pipeline status tracking, Simulation Speed and Accuracy. Performance of simulation test for three validation case studies (TI TMS320C62x, TI TMS320C64x and ST200) are reported.

High-level modeling and simulation of single-chip programmable heterogeneous multiprocessors

Heterogeneous multiprocessing is the future of chip design with the potential for tens to hundreds of programmable elements on single chips within the next several years. These chips will have heterogeneous, programmable hardware elements that lead to different execution times for the same software executing on different resources as well as a mix of desktop-style and embedded-style software. They will also have a layer of programming across multiple programmable elements forming the basis of a new kind of programmable system which we refer to as a Programmable Heterogeneous Multiprocessor (PHM). Current modeling approaches use instruction set simulation for performance modeling, but this will become far too prohibitive in terms of simulation time for these larger designs. The fundamental question is what the next higher level of design will be. The high-level modeling, simulation and design required for these programmable systems poses unique challenges, representing a break from traditional hardware design. Programmable systems, including layered concurrent software executing via schedulers on concurrent hardware, are not characterizable with traditional component-based hierarchical composition approaches, including discrete event simulation. We describe the foundations of our layered approach to modeling and performance simulation of PHMs, showing an example design space of a network processor explored using our simulation approach.

Embedded Processor Validation Environment Using a Cycle-Accurate Retargetable Instruction-Set Simulator

In the advent of System-on-Chip (SoC) technology, validation scope is further expanded from a single core to the system. Modules are also substituted by application specific instruction-set processors (ASIP) in order to raise abstraction level of systems from signals to instructions. As embedded processors are diversified according to their specific application, they suffer from an increasing number of irregular constraints and architectural idiosyncrasies. They also have control paths of pipeline which shows quite complicated timing. In order to alleviate these design complexities, validation must take retargetability and cycle-accuracy into consideration. We have thus proposed efficient embedded processor validation environment (EPVE) using a cycle-accurate retargetable instruction-set simulator (CARISS) as a reference model. The designed CARISS is based on an architecture description language (ADL), which provides improved retargetability for instruction-set machines. It also uses a scheduling method which can capture complex processor behavior more accurately than the ones used by the previous ADLs. We have applied the proposed EPVE for the 32bit embedded processors and investigated effectiveness of our approach by analyzing statistics on detected errors.

Embedded processor validation environment using a cycle-accurate retargetable instruction-set simulator

Embedded processor validation environment using a cycle-accurate retargetable instruction-set simulator

Heterogeneous system level co-simulation for the design of telecommunication systems

The advanced complexity and heterogeneity of modern telecommunication systems mostly lead to the incorporation of heterogeneous implementation technologies and design styles. Consequently, the design representation of such systems often requires the mixed use of distinct model of computations at different abstraction layers. Therefore, heterogeneous co-simulation is needed in order to enable the effective communication and interaction among the involved models of computation. This paper resolves this issue by proposing the heterogeneous co-modelling of telecom systems based on the combination of SDL semantics with C language running on an instruction set simulator, coupling in that way the specification and the first refinement steps of the co-design flow. The missing test link between the corresponding tools that support the SDL-C co-model is addressed by proposing a heterogeneous co-simulation scheme through the development of a mediator. Finally, the proposed methodology and the efficiency of the built environment are evaluated through a case study associated with the design of the MAC layer of the DECT telecom system.1,2

Power-Performance Simulation and Design Strategies for Single-Chip Heterogeneous Multiprocessors

Single chip heterogeneous multiprocessors (SCHMs) are becoming more commonplace, especially in portable devices where reduced energy consumption is a priority. The use of coordinated collections of processors which are simpler or which execute at lower clock frequencies is widely recognized as a means of reducing power while maintaining latency and throughput. A primary limitation of using this approach to reduce power at the system level has been the time to develop and simulate models of many processors at the instruction set simulator level. High-level models, simulators, and design strategies for SCHMs are required to enable designers to think in terms of collections of cooperating, heterogeneous processors in order to reduce power. Toward this end, this paper has two contributions. The first is to extend a unique, preexisting high-level performance simulator, the Modeling Environment for Software and Hardware (MESH), to include power annotations. MESH can be thought of as a thread-level simulator instead of an instruction-level simulator. Thus, the problem is to understand how power might be calibrated and annotated with program fragments instead of at the instruction level. Program fragments are finer-grained than threads and coarser-grained than instructions. Our experimentation found that compilers produce instruction patterns that allow power to be annotated at this level using a single number over all compiler-generated fragments executing on a processor. Since energy is power*time, this makes system runtime (i.e., performance) the dominant factor to be dynamically calculated at this level of simulation. The second contribution arises from the observation that high-level modeling is most beneficial when it opens up new possibilities for organizing designs. Thus, we introduce a design strategy, enabled by the high-level performance power-simulation, which we refer to as spatial voltage scaling. The strategy both reduces overall system power consumption and improves performance in our example. The design space for this design strategy could not be explored without high-level SCHM power-performance simulation.

Geometry engine architecture with early backface culling hardware

Most graphics accelerators waste valuable performance on transforming invisible vertices. To solve this problem, we have performed backface culling (BFC) earlier than transform and lighting (TnL). This paper proposes a survived vertex decision (SVD) algorithm to remove invisible vertices, and also suggests a geometry engine architecture that performs the early BFC with the SVD algorithm. This approach requires less hardware overhead. The SVD algorithm discards a vertex only if all triangles sharing that vertex are invisible in the mesh representing triangle lists or strips. The dedicated hardware performing the early BFC guarantees better performance in our approach, since it runs with the vertex engines in parallel. Particularly for a standalone engine, we introduce a unified architecture named the VP-Engine, which can perform the same tasks of the vertex engine and also handle the early BFC. Our architecture is designed using an instruction set simulator with a C++ library for cycle-accurate simulations. The early BFC removes half of the vertices that are transformed in the conventional approach, and as such the performance of our proposed architecture is twice as fast at maximum. Even with the sequential operations of early BFC and typical TnL, the VP-Engine is faster while the length of a vertex program is larger than 24.

ChronoSym: a new approach for fast and accurate SoC cosimulation

The early validation of modern SoC is not anymore feasible using traditional cycle-accurate cosimulations. These are based on the concurrent execution between SW running on multiple Instruction Set Simulators and HW simulators. The challenge is then speeding-up the simulation, without sacrificing the accuracy of traditional methods. The key contribution of this paper is a novel fast and accurate HW/SW cosimulation approach, allowing to handle large SoCs, while reducing the design cycle. The key underlying concepts are timed native SW execution, combined with detailed HW/SW interaction models. This approach is implemented in ChronoSym tool and applied to two real SoC applications.

A Universal Technique for Fast and Flexible Instruction-Set Architecture Simulation

Today, designers of next-generation embedded processors and software are increasingly faced with short product lifetimes. The resulting time-to-market constraints are contradicting the continually growing processor complexity. Nevertheless, an extensive design-space exploration and product verification is indispensable for a successful market launch. In the last decade, instruction-set simulators have become an essential development tool for the design of new programmable architectures. Consequently, the simulator performance is a key factor for the overall design efficiency. Motivated by the extremely poor performance of commonly used interpretive simulators, research work on fast compiled instruction-set simulation was started ten years ago. However, due to the restrictiveness of the compiled technique, it has not been able to push through in commercial products. In this paper, we tie up with our previous research on retargetable, compiled simulation techniques, and provide a discussion about their benefits and limitations using a particular compiled scheme, static scheduling, as an example. As a conclusion, we eventually present a novel retargetable simulation technique, which combines the performance of traditional compiled simulators with the flexibility of interpretive simulation. This technique is not limited to any class of architectures or applications and can be utilized from architecture exploration up to end-user software development. We demonstrate workflow and applicability of the so-called just-in-time cache-compiled simulation technique by means of state-of-the-art real-world architectures.

A formal concurrency model based architecture description language for synthesis of software development tools

Rapidly increasing design and manufacturing non-recurring engineering (NRE) costs are prompting a shift in electronic design from hardwired application specific integrated circuits (ASICs) to the use of software on programmable platforms. However, in order to minimize the power and performance overhead of such processors, we are seeing the introduction of domain or application specific processors such as network and communication processors. The design of such specialized processors requires software development tools such as simulators and compilers. In order to quickly develop these tools for multiple design points under consideration, it is highly desirable to have them synthesized from formal processor descriptions written in Architecture Description Languages (ADLs). In this paper, we present the Mescal Architecture Description Language (MADL). MADL features a two-layer structure, a core layer and an annotation layer. The core layer is based on a formal and flexible microprocessor model -- the operation state machine (OSM), which enables MADL to express the concurrency at the operation execution level for a wide range of architectures. We address the challenges faced in designing the core layer to combine the OSM model with techniques for achieving compact processor descriptions. The annotation layer features a generic syntax that allows creating annotation schemes to specify implementation dependent or tool specific information. To show the effectiveness of MADL, we present an MADL-based simulator synthesis framework that has been used to generate efficient cycle accurate simulators and instruction set simulators with very low development effort. We also describe our annotation schemes that enable the extraction of architecture properties for use in instruction scheduling and integer-linear-programming based register allocation. Our experimental results demonstrate the efficacy of MADL as a practical and promising language for the development of programmable platforms.

Automatic test program generation: a case study

Design validation is a critical step in the development of present-day microprocessors, and some authors suggest that up to 60% of the design cost is attributable to this activity. Of the numerous activities performed in different stages of the design flow and at different levels of abstraction, we focus on simulation-based design validation performed at the behavioral register-transfer level. Designers typically write assertions inside hardware description language (HDL) models and run extensive simulations to increase confidence in device correctness. Simulation results can also be useful in comparing the HDL model against higher-level references or instruction set simulators. Microprocessor validation has become more difficult since the adoption of pipelined architectures, mainly because you can't evaluate the behavior of a pipelined microprocessor by considering one instruction at a time; a pipeline's behavior depends on a sequence of instructions and all their operands.

Custom-Instruction Synthesis for Extensible-Processor Platforms

Efficiency and flexibility are critical, but often conflicting, design goals in embedded system design. The recent emergence of extensible processors promises a favorable tradeoff between efficiency and flexibility, while keeping design turnaround times short. Current extensible processor design flows automate several tedious tasks, but typically require designers to manually select the parts of the program that are to be implemented as custom instructions. In this work, we describe an automatic methodology to select custom instructions to augment an extensible processor, in order to maximize its efficiency for a given application program. We demonstrate that the number of custom instruction candidates grows rapidly with program size, leading to a large design space, and that the quality (speedup) of custom instructions varies significantly across this space, motivating the need for the proposed flow. Our methodology features cost functions to guide the custom instruction selection process, as well as static and dynamic pruning techniques to eliminate inferior parts of the design space from consideration. Furthermore, we employ a two-stage process, wherein a limited number of promising instruction candidates are first short-listed using efficient selection criteria, and then evaluated in more detail through cycle-accurate instruction set simulation and synthesis of the corresponding hardware, to identify the custom instruction combinations that result in the highest program speedup or maximize speedup under a given area constraint. We have evaluated the proposed techniques using a state-of-the-art extensible processor platform, in the context of a commercial design flow. Experiments with several benchmark programs indicate that custom processors synthesized using automatic custom instruction selection can result in large improvements in performance (up to 5.4/spl times/, an average of 3.4/spl times/), energy (up to 4.5/spl times/, an average of 3.2/spl times/), and energy-delay products (up to 24.2/spl times/, an average of 12.6/spl times/), while speeding up the design process significantly.

Profiling tools for hardware/software partitioning of embedded applications

Loops constitute the most executed segments of programs and therefore are the best candidates for hardware software partitioning. We present a set of profiling tools that are specifically dedicated to loop profiling and do support combined function and loop profiling. One tool relies on an instruction set simulator and can therefore be augmented with architecture and micro-architecture features simulation while the other is based on compile-time instrumentation of gcc and therefore has very little slow down compared to the original program We use the results of the profiling to identify the compute core in each benchmark and study the effect of compile-time optimization on the distribution of cores in a program. We also study the potential speedup that can be achieved using a configurable system on a chip, consisting of a CPU embedded on an FPGA, as an example application of these tools in hardware/software partitioning.

Systemc cosimulation and emulation of multiprocessor soc designs

SystemC is an open source C/C++ simulation environment that provides several class packages for specifying hardware blocks and communication channels. The design environment specifies software algorithmically as a set of functions embedded in abstract modules that communicate with one another and with hardware components via abstract communication channels. It enables transparent integration of instruction-set simulators and prototyping boards. The authors describe a simulation environment that targets heterogeneous multiprocessor systems. They are currently working to extend their methodology to more complex on-chip architectures.

Timed compiled-code functional simulation of embedded software for performance analysis of SOC design

A new timing generation method is proposed for the performance analysis of embedded software. The time stamp generation of input/output (I/O) accesses is crucial to performance estimation and architecture exploration in the timed functional simulation that simulates the whole design at a functional level with timing. A portable compiler is modified to generate time deltas which are the estimated cycle counts between two adjacent I/O accesses by counting the cycles of the intermediate representation (IR) operations and using a machine description that contains information on a target processor. Since the proposed method is based on the machine-independent IR of a compiler, the method can be applied to various processors by changing the machine description. The experimental results show that the proposed method is effective in that the average estimation error is about 2% and the maximum speed-up over the corresponding instruction-set simulators is about 300 times. The proposed method is also verified in a timed functional simulation environment.

An analysis of operating system behavior on a simultaneous multithreaded architecture

This paper presents the first analysis of operating system execution on a simultaneous multithreaded (SMT) processor. While SMT has been studied extensively over the past 6 years, previous research has focused entirely on user-mode execution. However, many of the applications most amenable to multithreading technologies spend a significant fraction of their time in kernel code. A full understanding of the behavior of such workloads therefore requires execution and measurement of the operating system, as well as the application itself.To carry out this study, we (1) modified the Digital Unix 4.0d operating system to run on an SMT CPU, and (2) integrated our SMT Alpha instruction set simulator into the SimOS simulator to provide an execution environment. For an OS-intensive workload, we ran the multithreaded Apache Web server on an 8-context SMT. We compared Apache's user- and kernel-mode behavior to a standard multiprogrammed SPECInt workload, and compared the SMT processor to an out-of-order superscalar running both workloads. Overall, our results demonstrate the microarchitectural impact of an OS-intensive workload on an SMT processor and provide insight into the OS demands of the Apache Web server. The synergy between the SMT processor and Web and OS software produced a greater throughput gain over superscalar execution than seen on any previously examined workloads, including commercial databases and explicitly parallel programs.

An analysis of operating system behavior on a simultaneous multithreaded architecture

This paper presents the first analysis of operating system execution on a simultaneous multithreaded (SMT) processor. While SMT has been studied extensively over the past 6 years, previous research has focused entirely on user-mode execution. However, many of the applications most amenable to multithreading technologies spend a significant fraction of their time in kernel code. A full understanding of the behavior of such workloads therefore requires execution and measurement of the operating system, as well as the application itself.To carry out this study, we (1) modified the Digital Unix 4.0d operating system to run on an SMT CPU, and (2) integrated our SMT Alpha instruction set simulator into the SimOS simulator to provide an execution environment. For an OS-intensive workload, we ran the multithreaded Apache Web server on an 8-context SMT. We compared Apache's user- and kernel-mode behavior to a standard multiprogrammed SPECInt workload, and compared the SMT processor to an out-of-order superscalar running both workloads. Overall, our results demonstrate the microarchitectural impact of an OS-intensive workload on an SMT processor and provide insight into the OS demands of the Apache Web server. The synergy between the SMT processor and Web and OS software produced a greater throughput gain over superscalar execution than seen on any previously examined workloads, including commercial databases and explicitly parallel programs.

An analysis of operating system behavior on a simultaneous multithreaded architecture

This paper presents the first analysis of operating system execution on a simultaneous multithreaded (SMT) processor. While SMT has been studied extensively over the past 6 years, previous research has focused entirely on user-mode execution. However, many of the applications most amenable to multithreading technologies spend a significant fraction of their time in kernel code. A full understanding of the behavior of such workloads therefore requires execution and measurement of the operating system, as well as the application itself.To carry out this study, we (1) modified the Digital Unix 4.0d operating system to run on an SMT CPU, and (2) integrated our SMT Alpha instruction set simulator into the SimOS simulator to provide an execution environment. For an OS-intensive workload, we ran the multithreaded Apache Web server on an 8-context SMT. We compared Apache's user- and kernel-mode behavior to a standard multiprogrammed SPECInt workload, and compared the SMT processor to an out-of-order superscalar running both workloads. Overall, our results demonstrate the micro-architectural impact of an OS-intensive workload on an SMT processor and provide insight into the OS demands of the Apache Web server. The synergy between the SMT processor and Web and OS software produced a greater throughput gain over superscalar execution than seen on any previously examined workloads, including commercial databases and explicitly parallel programs.

DyC: an expressive annotation-directed dynamic compiler for C

We present the design of DyC, a dynamic-compilation system for C based on run-time specialization. Directed by a few declarative user annotations that specify the variables and code on which dynamic compilation should take place, a binding-time analysis computes the set of run-time constants at each program point in the annotated procedure's control-flow graph; the analysis supports program-point-specific polyvariant division and specialization. The results of the analysis guide the construction of a run-time specializer for each dynamically compiled region; the specializer supports various caching strategies for managing dynamically generated code and mixes of speculative and demand-driven specialization of dynamic branch successors. Most of the key cost/benefit trade-offs in the binding-time analysis and the run-time specializer are open to user control through declarative policy annotations. DyC has been implemented in the context of an optimizing compiler, and initial results have been promising. The speedups we have obtained are good, and the dynamic-compilation overhead is among the lowest of any dynamic-compilation system, typically 20–200 cycles per instruction generated on a Digital Alpha 21164. The majority of DyC's functionality has been used to dynamically compile an instruction-set simulator. Only three annotations were required, but a few other changes to the program had to be made due to DyC's lack of support for static global variables. This deficiency and DyC's rudimentary support for partially static data structures are the primary obstacles to making DyC easy to use.