Instruction Set Design Research Articles

A quantitative study for Java microprocessor architectural requirements. Part I: Instruction set design

Java was designed for network programming. This imposes certain requirements on its virtual machine instruction set architecture and on designs that support Java. The purpose of this study is to carry out a behavioral analysis of the different aspects of Java instruction set architecture. This will help in establishing the hardware requirements for executing Java bytecodes. First, the bytecode interpreter was instrumented to include performance counters and statistics collectors. Then performance metrics were collected through benchmarking. Analyzing these data helps to identify performance-critical aspects that are candidates for hardware support, while less critical aspects can be left for software implementations. In this first part of our two-part paper, we study access patterns for data types, addressing modes, and instruction encoding. Recommendations for architectural requirements for Java processors will be made throughout this study.

Designing a NICE processor

The following article is a tutorial on CPU design aspects like instruction set design, etc. It covers in detail the design process which led to the NICE-processor (NICE is charmingly elegant), developed in 1997 (B. Ulmann, Computer Architecture News, October 1997). This architecture is very well suited for educational purposes in computer architecture since it employs a simple but very powerful orthogonal instruction set in conjunction with a true general purpose register set and versatile addressing modes. These features simplify the programming of NICE as well as its possible implementation in hardware.

Theory and algorithms for face hypercube embedding

We present a new matrix formulation of the face hypercube embedding problem that motivates the design of an efficient search strategy to find an encoding that satisfies all faces of minimum length. Increasing dimensions of the Boolean space are explored; for a given dimension constraints are satisfied one at a time. The following features help to reduce the nodes of the solution space that must be explored: candidate cubes instead of candidate codes are generated, cubes yielding symmetric solutions are not generated, a smaller sufficient set of solutions (producing basic sections) is explored, necessary conditions help discard unsuitable candidate cubes, early detection that a partial solution cannot be extended to be a global solution prunes infeasible portions of the search tree. We have implemented a prototype package minimum input satisfaction kernel (MINSK) based on the previous ideas and run experiments to evaluate it. The experiments show that MINSK is faster and solves more problems than any available algorithm. Moreover, MINSK is a robust algorithm, while most of the proposed alternatives are not. Besides most problems of the complete Microelectronics Center of North Carolina (MCNC) benchmark suite, other solved examples include an important set of decoder programmable logic arrays (PLA's) coming from the design of microprocessor instruction sets.

Providing a laboratory for instruction set design

Computer architecture classes do not provide students with laboratory experience in the design of instruction set architectures. Projects that compare designs have not been possible due to a lack of support software. The design and evaluation of a new instruction set requires an assembler, a symbolic debugger, and a statistics gatherer. Every new instruction set requires changes to all three programs. It would be unrealistic to expect that either students or instructor would (re)write such software in order to evaluate each new design. A new, flexible software package called the Instruction Set Testbed (IST) provides for the comparison of instruction set architectures without writing any of the support software. IST's table-driven assembler uses a student-supplied architecture definition to assemble programs. IST's interactive debugger and a statistics gatherer also have access to the architecture definition. This allows symbolic debugging of the assembly language programs and automatic histogramming of instruction usage in the student-defined architecture. IST has been used in both undergraduate and graduate architecture classes to investigate such topics as orthogonality, choice and number of operands, addressing modes, and RISC philosophy.

Evaluation of range-checking addressing modes and the architecture of FLATS2

FLATS2 is a cyclic pipeline computer, i.e., a kind of resource-shared MIMD computer. This paper presents the instruction set design and its realization. It is shown that efficient processings can be realized for the processings such as array processing. The result of evaluation for FLATS2 is shown and discussed. The instruction set of FLATS2 is an extension of the existing scalar instruction set. The addressing mode of FLATS2 includes the range-checking function, as well as the function to branch according to the result of check. When the access address is within the specified range, the operation is actually executed on the memory operand and the operation branches to the specified address. If the address is outside the range, the operation does not branch but proceeds to the next instruction. If all of those operations are executed by one instruction, the array processing in the numerical calculation and symbolic processing can be made efficient. In the iterative processing by a loop, for example, the time for the loop control can be combined and concealed by superposing the loop control on the memory access and execution of operation. As a result, data are supplied continuously to the arithmetic operator and a high numerical operation performance is realized. Furthermore, it is permitted in FLATS2 to execute more than one operation by an instruction using the composite instruction, which further improves the operation performance.

Toward a dataflow/von Neumann hybrid architecture

Dataflow architectures offer the ability to trade program level parallelism in order to overcome machine level latency. Dataflow further offers a uniform synchronization paradigm, representing one end of a spectrum wherein the unit of scheduling is a single instruction. At the opposite extreme are the von Neumann architectures which schedule on a task, or process, basis. This paper examines the spectrum by proposing a new architecture which is a hybrid of dataflow and von Neumann organizations. The analysis attempts to discover those features of the dataflow architecture, lacking in a von Neumann machine, which are essential for tolerating latency and synchronization costs. These features are captured in the concept of a parallel machine language which can be grafted on top of an otherwise traditional von Neumann base. In such an architecture, the units of scheduling, called scheduling quanta , are bound at compile time rather than at instruction set design time. The parallel machine language supports this notion via a large synchronization name space. A prototypical architecture is described, and results of simulation studies are presented. A comparison is made between the MIT Tagged-Token Dataflow machine and the subject machine which presents a model for understanding the cost of synchronization in a parallel environment.

Superoptimizer: a look at the smallest program

Given an instruction set, the superoptimizer finds the shortest program to compute a function. Startling programs have been generated, many of them engaging in convoluted bit-fiddling bearing little resemblance to the source programs which defined the functions. The key idea in the superoptimizer is a probabilistic test that makes exhaustive searches practical for programs of useful size. The search space is defined by the processor's instruction set, which may include the whole set, but it is typically restricted to a subset. By constraining the instructions and observing the effect on the output program, one can gain insight into the design of instruction sets. In addition, superoptimized programs may be used by peephole optimizers to improve the quality of generated code, or by assembly language programmers to improve manually written code.

Superoptimizer: a look at the smallest program

Given an instruction set, the superoptimizer finds the shortest program to compute a function. Startling programs have been generated, many of them engaging in convoluted bit-fiddling bearing little resemblance to the source programs which defined the functions. The key idea in the superoptimizer is a probabilistic test that makes exhaustive searches practical for programs of useful size. The search space is defined by the processor's instruction set, which may include the whole set, but it is typically restricted to a subset. By constraining the instructions and observing the effect on the output program, one can gain insight into the design of instruction sets. In addition, superoptimized programs may be used by peephole optimizers to improve the quality of generated code, or by assembly language programmers to improve manually written code.

Superoptimizer: a look at the smallest program

Given an instruction set, the superoptimizer finds the shortest program to compute a function. Startling programs have been generated, many of them engaging in convoluted bit-fiddling bearing little resemblance to the source programs which defined the functions. The key idea in the superoptimizer is a probabilistic test that makes exhaustive searches practical for programs of useful size. The search space is defined by the processor's instruction set, which may include the whole set, but it is typically restricted to a subset. By constraining the instructions and observing the effect on the output program, one can gain insight into the design of instruction sets. In addition, superoptimized programs may be used by peephole optimizers to improve the quality of generated code, or by assembly language programmers to improve manually written code.

On Instruction Sets and Their Fornmts

Central to instruction set design is the issue of the instruction format. We discuss some common format encoding techniques, and introduce a method of representing high-level language parse trees by means of formats that cover successively larger portions of a tree. We then introduce variations on the method that represent directed acyclic graphs as well as simple parse trees, and that encode constants in a special fashion. For a particular representation, we measure the number of times each format is executed to run a sample program to completion.

A systematic approach to the design and implementation of a computer instruction set

When selecting the instruction set for a computer family, the designer must consider several criteria. The design considerations leading to the final instruction set for a new computer are very seldom published. The purpose of this paper is twofold:• Discussion of the design and implementation criteria for an instruction set.• Proposal of a systematic approach for the design and implementation of an instruction set.

Keynote address - the processor instruction set

This keynote address contains a brief account of the arguements being advanced in favor of reduced instruction sets. These arguements have relevance both to single chip computers and to larger computers. Some comments are made on instruction set design from a compiler writer's point of view, and on the advantages to be gained from regarding the design of an instruction set and the code generator of the compiler as a single task.

Instruction set design issues relating to a static dataflow computer

In an effort to minimize traffic in the distribution network of a static dataflow machine the design of the system includes alternate data paths so that data movement may take place over “shorter” paths when it is permissible to do so. The main emphasis of this approach is to allow rapid transfer of data in sequential code segments residing in single memory blocks. This decreases crowding in the more expensive distribution network utilized by data that fans out to two or more blocks as required when more concurrent activity is to be initiated during the execution of the program. The objective of data movement minimization has also influenced the design of the instruction set. In this case, composite, that is, “multi-actor” instructions have been proposed as an effective strategy. This has been done without compromizing the utility of the instructions or overly increasing the time and space requirements of their execution. In the paper, these principles are illustrated by defining controlled instructions that are especially useful in the management of loops.

A language-oriented instruction set for the BALM language

The availability of microprogramming has increased interest in the design of instruction sets which are oriented towards particular higher-level languages (see (1), for example). We will refer to these as language-oriented instruction sets (or LOISs). In this paper we give a formal definition of a LOIS for the extendable language BALM. This LOIS, which we call MBALM, is used as the basis of the implementation of the current version of the language, BALM4. We will also compare two implementations of the MBALM instruction set, and outline briefly our experiences with them. The external description of BALM4 is given in detail elsewhere (2,3). Briefly, it is an extendable language with an Algol-like syntax and data-types integer, real, logical, string, pair (list), vector, identifier, procedure, and label. Type information is carried with all data-objects, and run-time type testing and conversion is done when necessary. Garbage collection and a run-time compiler are significant attributes of the system. Outlined below are some of the properties of the implementation, which was designed initially for reasons of simplicity and flexibility, but which illustrate some of the advantages of a LOIS-based system.

A microprogrammed satellite graphics system

A coordinated research effort in the area of interactive computer graphics using a host-satellite configuration is described. Central to the project is the use of a high-level programming language and two microprogrammable processors. The system as a whole is discussed, as well as the areas of interaction between the design of the satellite's instruction sets and the design of its operating system and the compiler.

R68-28 A Microprogrammed Implementation of EULER on IBM System/360 Model 30

The advent of microprogramming is likely to cause a major change in the way we use computers. The reason is that it provides a nearly complete decoupling between the efforts of computer design engineers and programmers. When the engineers provide a microcode that can be changed under program control, they will be able to pass on to the programmer a major portion of the design of the machine instruction set. The question is what the programmers will do with it when they get it.