Instruction Set Research Articles

Orchestrating iVR technology in an authentic classroom setting and its effects on factual knowledge, comprehension and transfer

AbstractAn increasing number of studies has observed that immersive virtual reality (iVR) technology using head-mounted displays (HMDs) can facilitate learning outcomes. However, most studies have been exploratory and were executed in laboratory settings instead of being implemented and orchestrated in authentic teaching settings. Furthermore, iVR design approaches based on learning theories in which learning objectives are in line with relevant curricula are still scarce. Thus, we conducted a study to provide insights from a perspective of instruction in authentic settings. We present the design of an iVR learning application that was aligned with curricula and that includes specific design features to foster relevant learning objectives. Orchestrated with additional learning material and learning activities, the iVR learning application was implemented and evaluated in an authentic teaching setting in the field of electrical engineering at a German vocational school. In order to investigate the effects of a lesson orchestrated around the iVR application, we conducted a study (n = 29) in a pre-post between-subject design in which we compared learning orchestrated around an iVR experience (iVR group n = 14) with learning in a more traditional setting consisting of a typical group task (control group n = 15). Participants were randomly assigned to one of the two groups; in both conditions, the same content was addressed. We compared group differences regarding four dependent variables: motivation, factual knowledge, comprehension and transfer. In both groups, we observed an increase in knowledge and comprehension. The gain in the iVR group was significantly stronger compared to the control group, but we observed no differences in motivation and transfer. We discuss our findings from a perspective of instruction in authentic settings, along with implications for instructional iVR technology design. Despite the high organizational effort still required to embed iVR technology into a classroom setting, we stress that instructional settings that entail complex cognitive and motor tasks can benefit in particular from agency as one of the main affordances provided by iVR technology. More research should be conducted in these settings, and additional research should focus on which design features make these iVR experiences effective, and how it can be assured that transfer of knowledge is also increased.

The role of cognitive load on interlimb differences in motor coordination in older adults.

While the dominant hand has been shown to have performance advantages over the nondominant hand, these interlimb differences have found to be dependent on task and biomechanical demands. The dynamic dominance hypothesis suggests that the left hemisphere is specialized for the control of intersegmental dynamics while the nondominant right hemisphere is specialized for postural control, in right-handers. In a real-world scenario, however, cognitive challenges might be expected to modulate these specialized behaviors. Therefore, we hypothesized that with increased cognitive load, lateralized motor control processes would become even more asymmetrical. We recruited 16 right-handed older adults (11 females, 5 males; 65.88 years ± 1.99 SEM) to perform 170 trials of a unilateral reaching task with each of their hands on the Kinereach system. In each trial, participants rapidly committed to memory a set of pictorial instructions before identifying and reaching for the correct object on a screen. The complexity of the task increased over the course of the experiment. Our results demonstrated higher reaction times in the right compared to left hand (p = 0.0004). Movements became increasingly curved and erroneous with cognitive load, but interlimb differences in movement quality were absent. We found higher joint cocontraction in the right compared to left arm (p < 0.05), but these differences were unaffected by cognitive load. Hence, with the addition of a cognitive load, we observed asymmetries in reaction time but not in joint coordination or movement quality. This highlights the role of cognitive load in modulating limb/hemisphere specializations for control processes.

A Different Kind of War: Deuteronomy 20:1–14 and Luke 10:1–24 in Dialogue

Abstract Passages promoting divinely approved violence permeate the biblical account. One Christian interpretative strategy, favored in premodern times but largely considered too arbitrary today, attempts to view these laws and stories of war as depicting battles against invisible forces of evil. This article attempts to strengthen this hermeneutical approach by focusing on a possible intertextual echo in Luke’s Gospel. It compares two sets of instructions—Israel’s military strategy against hostile cities in Deut 20:1–14 and the missionary blueprint, commanded by Jesus, for proclaiming the kingdom in Luke 10:1–24—and proposes that, in contrast to Israel’s rules for warfare, Luke’s account encourages Jesus’s disciples to approach the encountered cities nonviolently and turn their imagined swords against spiritual enemies. Consequently, the study suggests that the explored intertextual link might also function contrariwise and contribute toward establishing the metaphorical reading as a lasting option for interpreting biblical war narratives.

Combining quantum processors with real-time classical communication

Quantum computers process information with the laws of quantum mechanics. Current quantum hardware is noisy, can only store information for a short time and is limited to a few quantum bits, that is, qubits, typically arranged in a planar connectivity1. However, many applications of quantum computing require more connectivity than the planar lattice offered by the hardware on more qubits than is available on a single quantum processing unit (QPU). The community hopes to tackle these limitations by connecting QPUs using classical communication, which has not yet been proven experimentally. Here we experimentally realize error-mitigated dynamic circuits and circuit cutting to create quantum states requiring periodic connectivity using up to 142 qubits spanning two QPUs with 127 qubits each connected in real time with a classical link. In a dynamic circuit, quantum gates can be classically controlled by the outcomes of mid-circuit measurements within run-time, that is, within a fraction of the coherence time of the qubits. Our real-time classical link enables us to apply a quantum gate on one QPU conditioned on the outcome of a measurement on another QPU. Furthermore, the error-mitigated control flow enhances qubit connectivity and the instruction set of the hardware thus increasing the versatility of our quantum computers. Our work demonstrates that we can use several quantum processors as one with error-mitigated dynamic circuits enabled by a real-time classical link.

Graph-OPU: A Highly Flexible FPGA-Based Overlay Processor for Graph Neural Networks

Field-programmable gate arrays (FPGAs) are an ideal candidate for accelerating graph neural networks (GNNs). However, the FPGA redeployment process is time-consuming when updating or switching between diverse GNN models across different applications. Existing GNN processors eliminate the need for FPGA redeployment when switching between different GNN models. However, adapting matrix multiplication types by switching processing units decreases hardware utilization. In addition, the bandwidth of DDR limits further improvements in hardware performance. This article proposes a highly flexible FPGA-based overlay processor for GNN accelerations. Graph-OPU provides excellent flexibility and programmability for users, as the executable code of GNN models is automatically compiled and reloaded without requiring FPGA redeployment. First, we customize the compiler and instruction sets for the inference process of different GNN models. Second, we customize the datapath and optimize the data format in the microarchitecture to fully leverage the advantages of high bandwidth memory (HBM). Third, we design a unified matrix multiplication to handle both sparse-dense matrix multiplication (SpMM) and general matrix multiplication (GEMM), enhancing Graph-OPU performance. During Graph-OPU execution, the computational units are shared between SpMM and GEMM instead of being switched, which improves the hardware utilization. Finally, we implement a hardware prototype on the Xilinx Alveo U50 and test the mainstream GNN models using various datasets. Experimental results show that Graph-OPU achieves up to 1,654 \(\times\) and 63 \(\times\) speedup, as well as up to 5,305 \(\times\) and 422 \(\times\) energy efficiency boosts, compared to implementations on CPU and GPU, respectively. Graph-OPU outperforms state-of-the-art (SOTA) end-to-end overlay accelerators for GNN, reducing latency by an average of 1.36 \(\times\) and improving energy efficiency by 1.41 \(\times\) on average. Moreover, Graph-OPU exhibits an average 1.45 \(\times\) speed improvement in end-to-end latency over the SOTA GNN processor. Graph-OPU represents an in-depth study of an FPGA-based overlay processor for GNNs, offering high flexibility, speedup, and energy efficiency.

Using concept mapping to develop a curriculum for career studies

My goal in this paper is to offer a simple example of a career studies curriculum developed using the technique of concept mapping. In doing this, my intention is to help others construct their own courses, and so I would like to state quite clearly that what follows is simply an example of what a career studies curriculum might look like, it is not intended as a model or set of instructions. It is desirable, and in my view, essential, that course designers design their own courses and learning outcomes for their own contexts. I will make some preliminary remarks about concept mapping, explain my own career studies concept maps, and then use these to suggest eight workshops for use with participants. These workshop ideas will be relevant to designers of courses in career education, career development, employability, personal development, professional development, enterprise and career management skills.

Energy-efficient instruction compression with programmable dictionaries

To improve the energy efficiency of computation, accelerators trade off performance and energy consumption for flexibility. Fixed-function accelerators reach high energy efficiency, but are inflexible. Adding programmability via an instruction set architecture (ISA) incurs an energy consumption overhead, as instructions are fetched and decoded. To reduce it, hardware-controlled instruction caches and software-controlled components, such as loop buffers and (programmable) dictionaries improve the energy efficiency of instruction streams in embedded processors. Reducing the instruction overhead with code compression is well established and dictionary compression has been an effective approach due to its simplicity. Compared to static dictionaries, adding programmability improves the effectiveness. However, run-time-programmable dictionary compression and its effect on energy consumption has not been thoroughly studied. We describe a scheme to target energy efficiency by using fine-grained programmable dictionaries in embedded compute devices. Guided by compile-time analysis, the dictionary contents are changed during execution. On CHStone and Embench suites, our method reduces energy consumption on average by 11.4% and 3.8% with negligible run-time overhead. The addition of a loop buffer further reduces the energy consumption by 19.8% and 4.5% in the two suites. Our results indicate that programmable dictionary compression allows further energy reductions over an already highly tuned instruction stream.

SIMPLE Method for Plasmid Editing.

The development of molecular cloning techniques starting in the late 1960s created new tools to facilitate our understanding of gene function. Later advances in PCR and site-specific mutagenesis allowed researchers to efficiently dissect genes down to the single-nucleotide level. These methods have become virtually ubiquitous in nearly every biology laboratory. Recently, we developed an additional technique called SIMPLE (SapI/AarI incision-mediated plasmid editing), which allows for efficient deletions, short insertions (e.g., epitope tagging), and accurate mutations of episomal plasmids. SIMPLE cloning has a wide range of applications for molecular geneticists and adds a precision instrument to the biologist's toolbox. Here, we describe a detailed, step-by-step set of instructions for SIMPLE cloning.

Tiaozhuan: A General and Efficient Indirect Branch Optimization for Binary Translation

Binary translation enables transparent execution, analysis, and modification of the binary program, serving as a core technology that facilitates instruction set emulation, cross-platform compatibility of software, and program instrumentation. Handling indirect branch instructions is widely recognized as a significant performance bottleneck in binary translation. While the target of direct branch can be determined during the translation phase, indirect branch requires a run-time lookup from the guest program counter to the host program counter, significantly influencing the performance of translator. Although several methods have been proposed to accelerate this process, each guest indirect branch instruction still translates into approximately ten host instructions, resulting in considerable overhead. This paper introduces Tiaozhuan, which addresses this issue by employing two optimization schemes. Firstly, Full Address Mapping uses a larger address space to store address mappings from guest to host, effectively reducing the number of instructions required to lookup the target of an indirect branch. Secondly, Exception Assisted Branch Elimination further eliminates branch instructions that check target correctness of targets in the lookup process. These two approaches enable indirect branches target lookup to be completed within 1-2 instructions, noticeably decreasing the overhead of indirect branches. Compared to state-of-the-art mechanisms, the SPEC CPU2006 benchmark suite showed a reduction in the number of instructions by an average of 4.2%, with the highest observed performance improvement reaching 19.4% and an average increase of 3.9%.

Exploring facets of student motivation using a Bass Ackward strategy and the conceptual lens of self-determination theory

Motivational constructs have proliferated in educational psychology, reflecting the complexity of what moves people to engage and learn. In this exploratory research, we focused on students’ motivation for higher education. Our goal was to understand how a wide range of motives are empirically and conceptually related. We also examined how this diversity of motivational content relates to the motivational typology postulated by Self-Determination Theory (SDT). In Study 1, we extracted items from a broad collection of measures, formatted them with a common set of instructions, and administered them to multiple samples of current and former U.S. college students. Using Goldberg’s (2006) Bass Ackward factor-analytic method, we distilled twenty-six distinct facets that capture a wide variety of motivational contents. Multidimensional Scaling (MDS) suggested a dimension that resembled SDT’s continuum of relative autonomy, with some facets similar to amotivation and others falling along a range from less to more autonomous or volitional forms of motivation. In Study 2, we administered these provisionally labelled motivational facets alongside SDT’s regulatory styles and a set of external criteria covering multiple outcomes of interest in higher education. MDS analyses replicated the general pattern found in Study 1, recovering a dimension resembling SDT’s continuum of autonomy. Motivational facets were also associated with external criteria in a theoretically coherent manner. We discuss the implications of these exploratory findings for understanding the structure of self-reported motivation and for theory and measurement of student motivation.

Navigating assessment tensions in English-medium instruction (EMI) courses

While existing literature has delved into the critical role of assessment in effective teaching and highlighted the complexities it introduces to classroom dynamics, there is relatively little discussion about assessment issues in English-medium instruction (EMI) settings. This Researching EAP Practice article presents the distinct tensions faced by two EMI teachers and their coping strategies at a top Chinese university amid ongoing EMI curriculum reform since 2020. Drawing on findings from classroom observation and semi-structured interviews, the paper identifies three sources of EMI assessment tensions: the interplay between language and content, the clash between teachers' sense of responsibility and students' language proficiency, and the conflict between teachers’ assessment beliefs and institutional policies and cultures. The coping strategies suggested are categorized into language-related, pedagogical, and compromising approaches. The paper concludes with thoughtful pedagogical recommendations for alleviating these tensions, emphasizing the necessity for collaborative efforts among various stakeholders involved in the educational process.

Meaning-making in English-medium instruction science classroom interaction: from the systemic functional linguistics perspective

Abstract Teaching science in English is increasingly common worldwide. This study explores the role of language in science meaning-making during classroom interactions by drawing on video-recorded classroom observations of four biology lessons in secondary English medium instruction (EMI) settings in Hong Kong. Informed by systemic functional linguistics (SFL), we integrate classroom interaction analysis with Lemke’s approach to thematic analysis. The results reveal similar interactional patterns across full- and partial-EMI science classrooms, characterised by a lack of interactivity and authoritative teacher behaviour in selecting student responses to engage with. During extended initiation–response–feedback exchanges, teachers’ feedback on students’ responses appears to underscore the importance of teachers’ modified input – specifically input emphasising semantic relations within the field of biology – in developing students’ content knowledge and language skills. The implications of the findings for applying SFL pedagogies in EMI science classrooms to improve teacher–student interaction are discussed.

Conflict Management in Vector Register Files

The instruction set architecture (ISA) of vector processors operates on vectors stored in the vector register file (VRF) which needs to handle several concurrent accesses by functional units (FUs) with multiple ports. When the vector processor is running with high utilization, access conflicts become a major source of performance degradation. With a software model of a vector processor, we take a deep dive into the runtime impact of conflicts, their characteristics, and on ways to manage them, i.e., avoidance, resolution, and mitigation. For conflict avoidance, we study the existing approaches of banking with different static bank layouts and propose a dynamic bank layout to overcome their shortcomings. Our approach assigns newly written registers a temporarily unique starting bank. For conflict resolution, we compare different arbitration algorithms and optimize round-robin arbitration for mixed-width arithmetics by prioritizing wide operands. For conflict mitigation, operand queues (OPQs) of varying depths are studied. Our inventions are likely to increase the area efficiency of vector processors. Either, because they allow to use shallower operand queues (OPQs) while keeping the same performance, or reduce the area even further by using less banks, albeit at a performance impairment of 10 % or less. The insights of the study can further be applied to other shared-memory systems.

An Advanced Hardware Implementation of the Trial Division Algorithm for Dividers Utilizing RISC-V ISA

In this paper, we try to design a divider based on RISC-V instruction set architecture (ISA). Since the hardware design of the divider in the ALU is very important for the CPU to implement the arithmetic function. In view of the advantages of the trial division method in the division algorithm and the popularity of the RISC-V ISA, this paper attempts to design a trial division divider utilizing the RISC-V ISA. In this design, the principle of trial division, flow chart, state diagram, RISC-V instructions of division, whole divider module and logic will be designed in detail. To test the function and feasibility, the hardware description is carried out in the Verilog hardware description language (HDL). In this description, four division RISC-V instructions are integrated. Modelsim is used to verify and test the functionality of the divider. The test waveform is used as a result to verify the feasibility of the divider.

RISC-V Leads the Future: Evolution and Outlook of CPU Architecture

This essay mainly talked the development of CPU and some instruction set architecture based on RISCV. CPU is known as the Central Processing Unit, the main appliment is RISCV, Also the ARM architecture is characterized by a focus on the balance between low power consumption and high performance. Then X86, its significant advantage is its complex instruction set and excellent performance, so it can handle complex computational tasks. We also explore the Pipeline technology, it is a widely used parallel processing technology today. The design principle is to divide complex, multilevel combinational logic circuits into multiple levels. Then, we find some experiment data to explore our conclusion. We find that each has its own advantages and is better suited to different scenarios. In terms of performance, x86 offers superior capabilities but consumes more power, making it ideal for high-performance computing and server applications. ARM, on the other hand, excels in power efficiency and finds its primary use in mobile devices and embedded systems. RISC-V, known for its flexibility, allows for a balance between performance and power consumption based on specific requirements, making it suitable for highly customizable applications, IoT devices, and emerging high-performance computing markets. The advantages of each architecture in different fields depend on the specific application environment and demands placed on them.

The Ascendancy of RISC-V: An In-Depth Review of Its Open-Source Potential and Future Applications

Currently, the rapid advancement of RISC-V and the consequent changes in industry and market landscapes are capturing significant attention from various stakeholders. In recent years, there has been a notable increase in the number of companies and developers dedicating their efforts to researching and developing RISC-V technologies. In light of this trend, this paper aims to examine the global development of RISC-V, providing a comprehensive analysis of its progression on an international scale. It will compare RISC-V with other prominent instruction set architectures such as x86 and ARM, evaluating the relative merits and drawbacks of each. The paper will systematically organize and discuss relevant data to highlight RISC-V’s advantages and limitations. Furthermore, it will present an overview of existing RISC-V products and their applications across different sectors. Lastly, the paper will explore the future market potential of RISC-V, assessing how it might influence the industries related to chips and related markets in the coming years.

Design and Implementation of Digital Integrated Circuit Based CPU

This paper presents a simplified 16-bit CPU design and its implementation using digital integrated circuits developed with Verilog hardware description language, while emphasizing simulation through the EDA tool. This design puts more emphasis on the critical roles played by the data path and the control unit, executing key instructions including arithmetic operations such as addition, subtraction, bitwise logic, and conditional jumps. This structurally modular CPU is both functioning and stable in nature, allowing support for future enhancements and enhancements as well, thereby serving as an effective model towards an understanding of the principles of CPU design. The execution of these basic instructions puts the core of the CPU under test and reaffirms its proper operation in respect of the detailed instruction set, while its extensibility design confirms further improvement possibilities for future complex instructions as well as finite-state machine optimization for the control unit. The present work not only proves the possibility of creating a fully working CPU, using readily available bare minimum resources to implement a prototype, but is also a breakthrough in future research with CPU architecture. The obtained results will shed light on CPU functionality optimization and extension, being the ground for building more powerful and effective processors in the future.

ASIP Performance Enhancement by Hazard Control through Scoreboard.

The application-specific instruction set processor (ASIP) has been gradually accepted in AI, communication, media, game and industry control. The digital signal processor (DSP) is a typical ASIP, whose benefits include high performance in specific domains, low power consumption, high flexibility and low silicon consumption. One of the challenges for DSP design is to handle problems induced by datapath acceleration. The datapath acceleration (instruction fusion, black box instructions) induces control complexities. To most efficiently utilize hardware, control challenges can be summarized as RAW (Read-After-Write) handling, hardware hazard handling, and WAW (Write-After-Write) handling. Both an advanced compiler and hardware hazard handler can be used as solutions. In this paper, we introduced both solutions and exposed the benefits from the hardware solution. The benefits include utilizing low silicon to achieve higher performance and program memory reduction on chip. In summary, our solution only uses 0.91% extra silicon area yet achieves 32.75% performance improvement. So, the overall performance-to-cost ratio could be evaluated as 32%.

OphGLM: An ophthalmology large language-and-vision assistant

Vision computer-aided diagnostic methods have been used in early ophthalmic disease screening and diagnosis. However, the limited output formats of these methods lead to poor human–computer interaction and low clinical applicability value. Thus, ophthalmic visual question answering is worth studying. Unfortunately, no practical solutions exist before Large Language Models(LLMs). In this paper, we investigate the ophthalmic visual diagnostic interaction problem. We construct an ophthalmology large language-and-vision assistant, OphGLM, consisting of an image encoder, a text encoder, a fusion module, and an LLM module. We establish a new Chinese ophthalmic fine-tuning dataset, FundusTuning-CN, including the fundus instruction and conversation sets. Based on FundusTuning-CN, we establish a novel LLM-tuning strategy to introduce visual model understanding and ophthalmic knowledge into LLMs at a low cost and high efficiency. Leveraging the pre-training of the image encoder, OphGLM demonstrates strong visual understanding and surpasses open-source visual language models in common fundus disease classification tasks. The FundusTuning-CN enables OphGLM to surpass open-source medical LLMs in both ophthalmic knowledge and interactive capabilities. Our proposed OphGLM has the potential to revolutionize clinical applications in ophthalmology. The dataset, code, and models will be publicly available at https://github.com/ML-AILab/OphGLM.

Design of Low Power Control Unit for RISC-V Processor Core

This research work focuses on the development of a low-power decode logic for a RISC-V processor core with specifications. The goal is to create a controller that performs all six groups of instruction formats outlined in the RV32I Base Integer Instruction Set. The control unit is designed to decode a total of 13 instruction sets, allowing for a comprehensive range of operations. A single instruction pipeline approach is implemented in the design to optimize performance. The synthesis of the design is carried out using the 32 nm standard library, resulting in a maximum operating frequency of 666.67 MHz. To further enhance power efficiency, clock gating techniques are employed, leading to a reduction in power consumption by 18.72 % from 112.15 µW to 91.45 µW. Additionally, the layout of the design is optimized, resulting in an area of 354.74 mm2. The successful development of this low-power decode logic demonstrates its potential for integration into larger RISC-V processor cores. Future enhancements can include expanding the instruction decoding capability to encompass the full range of 47 instructions in the RV32I Base Integer Instruction Set, as well as exploring additional pipeline stages to further improve performance. The results achieved in this project contribute to the ongoing pursuit of power-efficient and high-performance processor designs based on the RISC-V architecture.