Instruction Cycle Time Research Articles

VLSI Implementation of High Speed-Low Power-Area Efficient Multiplier Using Modified Vedic Mathematical Techniques

Background: Since multiplication dominates the execution time of most DSP algorithms, there is a need of high speed, area efficient and power efficient multiplier. Also, many patents emphasize on the fact that multiplication time is still the dominant factor in determining the instruction cycle time of a DSP chip. Hence, there is a need for high speed- low power multipliers. This can be achieved by using the concept of Vedic Mathematics as multipliers based on Vedic Mathematics is one of the fast and low power multiplier Urdhva tiryakbhyam, Nikhilam, sutras forms the basic Vedic formulas in the design of Vedic multipliers. Keywords: Vedic sutra, karatsuba algorithm, DFT, array multiplier, radix-4 technique, urdhva tryagbhyam sutra.

Comparison of RISC and DSP processors for a transform domain implementation of the discrete wavelet transform

In this paper we analyse the efficiency of an implementation of the discrete wavelet transform using a modified transform domain approach on several classes of DSP and RISC processors. The recently emerged discrete wavelet transform is faster than a standard Fast Fourier Transform, yet it is computationally intensive since the number of computations required increases with the number of octaves. A computationally efficient transform domain implementation of the discrete wavelet transform for wavelets of length 20 or greater is described in this paper. To compare the efficiency of RISC and DSP processors for this method, we first analyse the implementation of a radix 2, radix 4, and split radix Fast Fourier Transform algorithm on some of the latest DSP and RISC processors. This is followed by an analysis of the implementation of complex multiplication on the processors under considerations. We show that both DSP and RISC processors need the same number of instruction cycles to execute a complex multiplication. Finally, we show that those RISC processors which have their instruction cycle time equal to 85% of a DSP processor's instruction cycle time, give better performance than DSP processors for implementing the wavelet transform using a longer wavelet.

Efficient superscalar performance through boosting

The foremost goal of superscalar processor design is to increase performance through the exploitation of instruction-level parallelism (ILP). Previous studies have shown that speculative execution is required for high instruction per cycle (IPC) rates in non-numerical applications. The general trend has been toward supporting speculative execution in complicated, dynamically-scheduled processors. Performance, though, is more than just a high IPC rate; it also depends upon instruction count and cycle time. Boosting is an architectural technique that supports general speculative execution in simpler, statically-scheduled processors. Boosting labels speculative instructions with their control dependence information. This labelling eliminates control dependence constraints on instruction scheduling while still providng full dependence information to the hardware. We have incorporated boosting into a trace-based, global scheduling algorithm that exploits ILP without adversely affecting the instruction count of a program. We use this algorithm and estimates of the boosting hardware involved to evaluate how much speculative execution support is really necessary to achieve good performance. We find that a statically-scheduled superscalar processor using a minimal implementation of boosting can easily reach the performance of a much more complex dynamically-scheduled superscalar processor.

Long pipelines in single-chip digital signal processors-concepts and case study

The effectiveness of long pipelines in single-chip digital signal processors for complex algorithms was studied using a processor model with 25 pipeline stages. The processor is based on a Harvard architecture. Pipelining is used to reduce the instruction cycle time compared to current signal processors. Key features of the processor model are data-stationary pipeline control, local resolution of pipeline hazards with buffering, multiple branch prediction, a mixed relative-incremental addressing scheme, and asynchronous communication between pipeline and environment. The processor is implemented as a software model. The results show that high pipeline utilization can be achieved for a variety of algorithms leading to a significantly higher performance than achieved by conventional single-chip signal processors with Harvard architecture. >

A 24-b 50-ns digital image signal processor

A 50-ns digital image signal processor (DISP)-an image/video application-specific VLSI chip-is discussed. This chip integrates 538 K transistors and dissipates 1.4 W at a 40-MHz clock. It is based on a 24-b fixed-point architecture with a five-stage pipeline. The DISP features a real-time processing capability realized by an enhanced parallel architecture, video-oriented data processing functions, and an instruction cycle time that is typically 35 ns, and 50 ns at worst. This 50-ns cycle time allows the DISP to execute mor than 60-million operations per second (MOPS). High-density 1.0- mu m CMOS technology allows numerous on-chip features, including specified resources optimized for image processing. This allows a flexible hardware implementation of various algorithms for picture coding. Several circuit design techniques that are intended to attain a fast instruction cycle are reviewed, including distributed instruction decoding and a hierarchical clocking circuit. The LSI has been designed by the extensive use of a cell-based design method. The processor incorporates a sophisticated testing function compatible with a cell-based design environment.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A dynamic programming processor for speech recognition

A dynamic programming processor with parallel and pipeline architecture is described. A 2- mu m CMOS technology was applied to the DP processor, which is composed of 127309 transistors on a 7.17*8.62-mm/sup 2/ die and is housed in an 84-pin PLCC (plastic leaded chip carrier) or PGA (pin grid array) package. The clock frequency is 20 MHz, and the instruction cycle time is 100 ns. Precise electrical simulations permitted the safe use of nonstandard logic and area and power reduction. Implementation of a direct access to all internal registers has proven useful for chip test and software development. A system using one DP processor has given very good results on a wide variety of applications and 0.48% error rate on tests with standard NATO tapes. These results are significantly better than those published for other systems on the same tests. >

A microprogrammable real-time image processor

A microprogrammable real-time image signal processor (RISP) designed for use in general-purpose local image processing is described. The processor, using a novel architecture and high-speed bipolar technology, has achieved an instruction cycle time as fast as 20 ns. This processor is composed of a special local image register, arithmetic units, multiplier/divider, and a microprogramming unit. The fabrication relies on a bird's beak-free oxide isolation technology and a self-alignment technology to form the emitter and the base in ultradense ICs. The RISP, containing about 45000 elements, has been built on a silicon chip of 7.1*7.0 mm/sup 2/. Its power dissipation is 2.5 W. >

A 20-ns CMOS micro DSP core for video-signal processing

A programmable 8-b digital signal processor core with an instruction cycle time of 20 ns is developed. A 37.5-mm chip is fabricated by advanced 1.0- mu m double-level-metal CMOS technology. This processor has a reconfigurable high-speed data path supporting several multiply/accumulate function, including 16-tap linear-phase transversal filtering, high-speed adaptive filtering, and eight-point discrete cosine transformation. To provide high-speed operation within the chip, a programmable phase-locked loop circuit is built on the chip. This circuit generates a high-speed clock, which is a multiple of the system clock fed from outside, and is synchronized to the system clock. >

Reduced instruction set computers

Reduced instruction set computers aim for both simplicity in hardware and synergy between architectures and compilers. Optimizing compilers are used to compile programming languages down to instructions that are as unencumbered as microinstructions in a large virtual address space, and to make the instruction cycle time as fast as possible.

A 24-bit microprocessor for data communication systems designed on the basis of a general cell library

A 24-bit microprogrammed processor with 200 ns instruction cycle time has been realized as an experimental special purpose VLSI chip. The design was based on a general cell library and a set of advanced CAD tools. The technology used is a 3 /spl mu/m silicon gate, n-channel, single metallization MYMOS process. The chip integrates 9400 gate functions plus a 256/spl times/27 bit static RAM on 78.5 mm/SUP 2/.

A 1.5 V CMOS 4-bit microcomputer needs only 100 /spl mu/W

Describes a new 4-bit microcomputer fabricated using a low-power silicon gate CMOS process and working from a supply voltage down to 1.2 V. The /spl mu/C can directly drive up to seven 3:1 multiplexed LCD digits, scan up 48 keys, and perform 4-bit handshaking data transfer with external devices. 16-bit, single-word instructions and eight stack levels permit efficient use of the 640-word ROM. Operating from a 4.19 MHz crystal, the device has an instruction cycle time of 15 /spl mu/s. An operating power of 100 /spl mu/W at 1.5 W makes the chip ideal for performing control and timing functions in battery operated applications.

A single chip digital signal processor and its application to real-time speech analysis

A single chip high-performance digital signal processor (HSP) has been developed for speech, telecommunication, and other applications. The HSP uses 3 μm CMOS technology and its architecture features floating point arithmetic and pipeline structure. By adoption of floating point arithmetic, data covering a wide dynamic range (up to 32 bits) can be manipulated. The input clock frequency is 16 MHz, and the instruction cycle time is 250 ns. Efficient signal processing instructions and a large internal memory (program ROM: 512 words; data RAM: 200 words; data ROM: 128 words) make it possible to construct a compact speech analysis circuit by the LPC (PARCOR) method with two HSP's. This paper describes HSP architecture, LSI design, and a speech analysis application.

A Single Chip Digital Signal Processor and Its Application to Real-Time Speech Analysis

A single chip high-performance digital signal processor (HSP) has been developed for speech, telecommunication, and other applications. The HSP uses 3 µm CMOS technology and its architecture features floating point arithmetic and pipeline structure. By adoption of floating point arithmetic, data covering a wide dynamic range (up to 32 bits) can be manipulated. The input clock frequency is 16 MHz, and the instruction cycle time is 250 ns. Efficient signal processing instructions and a large internal memory (program ROM: 512 words; data RAM: 200 words; data ROM: 128 words) make it possible to construct a compact speech analysis circuit by the LPC (PARCOR) method with two HSP's. This paper describes HSP architecture, LSI design, and a speech analysis application.

Design of a binary coded decimal integer arithmetic unit

With the increased availability of microprocessors and microcomputers the design engineer has at his disposal the components necessary to design data analysis and control systems at a substantial cost savings over larger computer systems. In many cases, the choice between a computer, minicomputer and microcomputer is based on the speed at which arithmetic functions can be performed. In systems where Binary Coded Decimal (BCD) is a convenient form of data handling, the added overhead of BCD to binary and binary to BCD conversions decreases system performance. This paper describes a hardware BCD addition, subtraction, multiplication and division unit, which performs addition, subtraction and multiplication at speeds greater than the instruction cycle time of most mini and microcomputers (<1 μs, for a 4 digit × 4 digit operation.) and division in less than 10μs. The paper describes the algorithms and hardware utilized in the implementation of the arithmetic unit and discusses interface mechanisms for connecting the unit to a microcomputer.

High Speed Microprocessor Based System for Drift Chamber Data Acquisition

An 8×300 microprocessor with a 250 nsec., instruction cycle time was used to scan data from 512 drift chamber wires, and send only valid data to a central computer, all in less than 2 milsec. The speed, size, cost performance trade-offs which influenced the choice of data organization, scan method and electronics will be presented. Factors influencing the selection of the 8×300 as the microprocessor best suited for this application will be mentioned. Operation of hardware and software will be discussed, touching on speed vs. memory requirements. Included will be a brief discussion of microprocessor development systems.

A Radiation-Hard CMOS/SOS ALU

A radiation-hard CMOS/SOS technology has been used to fabricate a complex LSI circuit containing over 2200 transistors. The circuit is an eight bit wide arithmetic and logic unit (ALU) slice. This paper describes the results of electrical, temperature, and radiation tests on the ALU circuit. An instruction cycle-time of less than 240 ns was achieved for nominal operation at +11V and 25° C. This time increases to 300 ns at 125° C. After irradiation to 106 rads (Si) under bias, operation was degraded only slightly. The 25° C and 125° C postradiation cycle times were within 320 and 360 ns, respectively. Radiation tolerance from part to part and lot to lot was excellent, thus demonstrating the applicability of radiation hard CMOS/SOS to LSI circuitry.