Instruction Count Research Articles

Performance analysis of congestion-aware Q-routing algorithm for network on chip

<p>A network on chip’s performance is greatly impacted by network congestion due to the substantial increase in latency and energy utilized. Designing routing strategies that keep the network informed of the status of traffic is made easier by machine learning techniques. In this work, a reinforcement-based congestion-aware Q-routing (CAQR) technique has been presented. The proposed algorithm performed better in comparison to the conventional XY routing method tested against the SPEC CPU2006 benchmark suite in the gem5 NoC simulator tool. The suite used has 4 benchmarks, namely, namd, lbm, leslie3d and bzip2 which can be used for the cores in the network in any combination. The tests were run with 16 cores on a 44 network with the maximum instruction count supported by the system (here 5,000). The proposed Q-routing algorithm showed an average of 19% reduction for benchmark simulation as compared to the Dimension-ordered (X-Y) routing for readings of average packet latency which is a crucial factor in determining a network’s efficiency. The analysis also shows an average reduction of 24%, 10%, 23% and 47% in terms of average packet network latency, average flit latency, average flit network latency and average energy consumption across various benchmarks.</p>

Effective Stack Wear Leveling for NVM

With the rapid growth of data processed by computer systems, Non-Volatile Memory (NVM), represented by Phase Change Memory (PCM), is regarded as a promising nextgeneration storage technology as it offers superior advantages over DRAM. However, PCM suffers from a severe write durability problem, leading to an extremely short lifespan under the uneven write patterns of real-world programs. We observe that loops are one of the primary causes of uneven writes on the stack. To alleviate this problem, we present Loop2Recursion, a compiler-assisted stack wear leveling technique that automatically transforms loops into recursive functions. In addition, we propose several optimizations to reduce the stack sizes and instruction counts of the generated recursive functions, two schemes to limit recursion depth, and selective loop transformation for cache-enabled architectures. Experimental results demonstrate that Loop2Recursion outperforms state-of-the-art methods by significantly improving stack wear leveling with a greatly reduced performance overhead.

Auto-tuning Fixed-point Precision with TVM on RISC-V Packed SIMD Extension

Today, as deep learning (DL) is applied more often in daily life, dedicated processors such as CPUs and GPUs have become very important for accelerating model executions. With the growth of technology, people are becoming accustomed to using edge devices, such as mobile phones, smart watches, and VR devices in their daily lives. A variety of technologies using DL are gradually being applied to these edge devices. However, there is a large number of computations in DL. It faces a challenging problem how to provide solutions in the edge devices. In this article, the proposed method enables a flow with the RISC-V Packed extension (P extension) in TVM. TVM, an open deep learning compiler for neural network models, is growing as a key infrastructure for DL computing. RISC-V is an open instruction set architecture (ISA) with customized and flexible features. The Packed-SIMD extension is a RISC-V extension that enables subword single-instruction multiple-data (SIMD) computations in RISC-V architectures to support fallback engines in AI computing. In the proposed flow, a fixed-point type that is supported by an integer of 16-bit type and saturation instructions is added to replace the original 32-bit float type. In addition, an auto-tuning method is proposed to use a uniform selector mechanism (USM) to find the binary point position for fixed-point type use. The tensorization feature of TVM can be used to optimize specific hardware such as subword SIMD instructions with RISC-V P extension. With our experiment on the Spike simulator, the proposed method with the USM can improve performance by approximately 2.54 to 6.15× in terms of instruction counts with little accuracy loss.

OCCAM-v2: Combining Static and Dynamic Analysis for Effective and Efficient Whole-program Specialization

OCCAM-v2 leverages scalable pointer analysis, value analysis, and dynamic analysis to create an effective and efficient tool for specializing LLVM bitcode. The extent of the code-size reduction achieved depends on the specific deployment configuration. Each application that is to be specialized is accompanied by a manifest that specifies concrete arguments that are known a priori, as well as a count of residual arguments that will be provided at runtime. The best case for partial evaluation occurs when the arguments are completely concretely specified. OCCAM-v2 uses a pointer analysis to devirtualize calls, allowing it to eliminate the entire body of functions that are not reachable by any direct calls. The hybrid analysis feature can handle cases that are challenging for static analysis, such as input loops, string processing, and external data (in files, for example). On the suite of evaluated programs, OCCAM-v2 was able to reduce the instruction count by 40.6 percent on average, taking a median of 2.4 seconds.

Compiling CNNs with Cain: focal-plane processing for robot navigation

Focal-plane Sensor-processors (FPSPs) are a camera technology that enables low power, high frame rate computation in the image sensor itself, making them suitable for edge computation. To fit into the sensor array, FPSPs are highly resource-constrained, with limited instruction set and few registers - which makes developing complex algorithms difficult. In this work, we present Cain, a compiler for convolutional filters that targets SCAMP-5, a general-purpose FPSP. Cain generates code to evaluate multiple convolutional kernels at the same time. It generates code that avoids the need for hardware multipliers, while orchestrating the exploitation of common sub-terms—leading to a large reduction in instruction count compared to both straightforward and prior optimized approaches. We demonstrate the capability enabled by Cain on SCAMP-5 with robotic navigation for near-sensor high-speed and low-power computation, by using Cain to implement a neural network on the focal plane.

Mechanisms for Precise Virtual Time Advancement in Network Emulation

Network emulators enable rapid prototyping and testing of applications. In a typical emulation, the execution order and process execution burst lengths are managed by the host platform’s operating system, largely independent of the emulator. Timerbased mechanisms are typically used, but the imprecision of timer firings introduces imprecision in the advancement of time. This leads to statistical variation in behavior that is not due to the model. This article describes an open-source tool called Kronos, which provides a set of mechanisms for precise instruction-level tracking of process execution and control over execution order of containers, thus improving the mapping of executed behavior to advancement in time. This, and control of execution and placement of emulated processes in virtual time make the behavior of the emulation independent of the CPU resources of the platform that hosts the emulation. Under Kronos each process has its own virtual clock that is advanced based on a count of the number of \( \times \) 86 assembly instructions executed by its children. Two types of instruction counting techniques are discussed: (1) hardware-assisted mechanisms that are transparent to the executing application and (2) binary instrumentation-assisted mechanisms that modify the executing binary. We analyze the overheads associated with each approach and experimentally demonstrate the impact of Kronos’ time advancement precision by comparing it against emulations that, like Kronos, are embedded in virtual time, but unlike Kronos rely on Linux timers to control virtual machines and measure their progress in virtual time. We present two useful applications where Kronos aids in generating high-fidelity emulation results at low hardware costs: (1) analyzing protocol performance and (2) enabling analysis of cyber physical control systems. We also discuss limitations associated with simple linear conversions between instruction counts and ascribed virtual time and develop and evaluate more accurate virtual time conversion models.

Temporal characterization of memory access behaviors in SPEC CPU2017 workloads: Analysis and synthesis

The SPEC CPU2017 benchmark suite has received wide attention in both academia and industry. However, few work have studied the memory behaviors in SPEC CPU2017 workloads from a time dependence perspective. We run all SPEC CPU2017 benchmarks and collect 43 memory traces. This paper examines the correlation of memory access intervals in all SPEC CPU2017 workloads. The results show that there is a certain degree of correlation in the majority of the SPEC CPU2017 applications (79%). This observation differs from the SPEC CPU2006 in which the correlation of access behavior only exists in a small number of applications (27%). This phenomenon may be associated with an order-of-magnitude increase in the average instruction count in SPEC CPU2017. For each of 34 SPEC CPU2017 workloads with a certain degree of correlation, this paper estimates the Hurst parameters to test the self-similar property statistically. All Hurst parameters estimated are greater than 0.5, confirming the existence of self-similarity in SPEC CPU2017 workloads. We further deploy a versatile memory trace generator based on the inputs measured from the collected SPEC CPU2017 trace data. Experimental results show that the proposed model is robust for the memory access synthesis of various SPEC CPU2017 applications, and can accurately characterize the burstiness of memory access behaviors in SPEC CPU2017 workloads and more faithful than conventional models.

SUGAR: Speeding Up GPGPU Application Resilience Estimation with Input Sizing

As Graphics Processing Units (GPUs) are becoming a de facto solution for accelerating a wide range of applications, their reliable operation is becoming increasingly important. One of the major challenges in the domain of GPU reliability is to accurately measure GPGPU application error resilience. This challenge stems from the fact that a typical GPGPU application spawns a huge number of threads and then utilizes a large amount of potentially unreliable compute and memory resources available on the GPUs. As the number of possible fault locations can be in the billions, evaluating every fault and examining its effect on the application error resilience is impractical. Application resilience is evaluated via extensive fault injection campaigns based on sampling of an extensive fault site space. Typically, the larger the input of the GPGPU application, the longer the experimental campaign. In this work, we devise a methodology, SUGAR (Speeding Up G PGPU Application Resilience Estimation with input sizing), that dramatically speeds up the evaluation of GPGPU application error resilience by judicious input sizing. We show how analyzing a small fraction of the input is sufficient to estimate the application resilience with high accuracy and dramatically reduce the duration of experimentation. Key to our estimation methodology is the discovery of repeating patterns as a function of the input size. Using the well-established fact that error resilience in GPGPU applications is mostly determined by the dynamic instruction (DI) count at the thread level, we discover the patterns that allow to accurately predict application error resilience for arbitrarily large inputs. For the cases that we examine in this paper, this new resilience estimation provides significant speedups (up to 1336 times) and 97.0 on the average, while keeping estimation errors to less than 1%, for details see the full version of this SIGMETRICS paper.

Experimental Analysis Of Optimization Flags In Gcc

Compiler performance is critical in improving the overall functionality of a system. Evaluating compiler efficiency is a difficult process because it necessitates the completion of many steps in order to obtain the best result. In this paper, the performance of the GCC compiler's standard optimization levels is experimentally analyzed using the Linux perf tool with selected Collective Benchmark (CBench-V1.1) programs. The analysis is carried out with two parameters, execution time and instruction count which contributes majorly towards the parameters considered for satisfying the compilers design's objective of increasing the speed of execution and minimizing utilization of the memory of a program.

SUGAR

As Graphics Processing Units (GPUs) are becoming a de facto solution for accelerating a wide range of applications, their reliable operation is becoming increasingly important. One of the major challenges in the domain of GPU reliability is to accurately measure GPGPU application error resilience. This challenge stems from the fact that a typical GPGPU application spawns a huge number of threads and then utilizes a large amount of potentially unreliable compute and memory resources available on the GPUs. As the number of possible fault locations can be in the billions, evaluating every fault and examining its effect on theapplication error resilience is impractical. Application resilience is evaluated via extensive fault injection campaigns based on sampling of an extensive fault site space. Typically, the larger the input of the GPGPU application, the longer the experimental campaign. In this work, we devise a methodology, SUGAR (Speeding Up GPGPU Application Resilience Estimation with input sizing), that dramatically speeds up the evaluation of GPGPU application error resilience by judicious input sizing. We show how analyzing a small fraction of the input is sufficient to estimate the application resilience with high accuracy and dramatically reduce the duration of experimentation. Key of our estimation methodology is the discovery of repeating patterns as a function of the input size. Using the well-established fact that error resilience in GPGPU applications is mostly determined by the dynamic instruction count at the thread level, we identify the patterns that allow us to accurately predict application error resilience for arbitrarily large inputs. For the cases that we examine in this paper, this new resilience estimation mechanism provides significant speedups (up to 1336 times) and 97.0 on the average, while keeping estimation errors to less than 1%.

Microprocessors KOMDIV for High Performance Embedded Systems

The problems of creating of high-performance embedded computing systems based on microprocessors KOMDIV is considered. Processor performance is dependent upon three characteristics: clock cycle, clock cycles per instruction, and instruction count. These characteristics for microprocessors KOMDIV are optimized using parameter performance/power consumption and requirements of embedded systems.

TargO: A Targeted Obfuscator for Android Applications

In the world of fast-growing technology and an ever-increasing number of cyber-attacks, protecting secrets have become essential as well as costly. One of the techniques that have stayed afloat against the test of time is code obfuscation. Organizations still rely on obfuscation to hide their intellectual property from easy reverse engineering. But along with its effectiveness, obfuscation also brings with it performance overhead of the software. In this paper, we propose TargO, a targeted obfuscator that aims at reducing the performance overhead without compromising the advantage obfuscation provides. In TargO, developers are given a choice of obfuscating only the sensitive portions of the application. The effectiveness of this technique is then analysed by comparing it with existing obfuscators. Software code metrics such as cyclomatic complexity, execution time and instruction count was used to quantify, measure and compare the effects of the existing obfuscators against TargO. This comparison and further analysis help to confirm the fact that targeted obfuscation is equally or better effects so that reverse engineering can be deterred.

Multi-objective Exploration for Practical Optimization Decisions in Binary Translation

In the design of mobile systems, hardware/software (HW/SW) co-design has important advantages by creating specialized hardware for the performance or power optimizations. Dynamic binary translation (DBT) is a key component in co-design. During the translation, a dynamic optimizer in the DBT system applies various software optimizations to improve the quality of the translated code. With dynamic optimization, optimization time is an exposed run-time overhead and useful analyses are often restricted due to their high costs. Thus, a dynamic optimizer needs to make smart decisions with limited analysis information, which complicates the design of optimization decision models and often causes failures in human-made heuristics. In mobile systems, this problem is even more challenging because of strict constraints on computing capabilities and memory size. To overcome the challenge, we investigate an opportunity to build practical optimization decision models for DBT by using machine learning techniques. As the first step, loop unrolling is chosen as the representative optimization. We base our approach on the industrial strength DBT infrastructure and conduct evaluation with 17,116 unrollable loops collected from 200 benchmarks and real-life programs across various domains. By utilizing all available features that are potentially important for loop unrolling decision, we identify the best classification algorithm for our infrastructure with consideration for both prediction accuracy and cost. The greedy feature selection algorithm is then applied to the classification algorithm to distinguish its significant features and cut down the feature space. By maintaining significant features only, the best affordable classifier, which satisfies the budgets allocated to the decision process, shows 74.5% of prediction accuracy for the optimal unroll factor and realizes an average 20.9% reduction in dynamic instruction count during the steady-state translated code execution. For comparison, the best baseline heuristic achieves 46.0% prediction accuracy with an average 13.6% instruction count reduction. Given that the infrastructure is already highly optimized and the ideal upper bound for instruction reduction is observed at 23.8%, we believe this result is noteworthy.

Static Profiling of Assembly Code Performance and Optimization Effectiveness using Instructions Performed and Program Latency

Software program optimization for improved execution speed can be achieved through modifying the program. Programs are usually written in high level languages then translated into low level assembly language. More coverage of optimization and performance analysis can be performed on low level than high level language. Optimization improvement is measured in the difference in program execution performance. Several methods are available for measuring program performance are classified into static approaches and dynamic approaches. This paper presents an alternative method of more accurately measuring code performance statically than commonly used code analysis metrics. New metrics proposed are designed to expose effectiveness of optimization performed on code, specifically unroll optimizations. An optimization method, loop unroll is used to demonstrate the effectiveness of the increased accuracy of the proposed metric. The results of the study show that measuring Instructions Performed and Instruction Latency is a more accurate static metric than Instruction Count and subsequently those based on it.

IPA: an Instruction Profiling–Based Micro-architectural Side-Channel Attack on Block Ciphers

Hardware performance counters (HPCs) are present in most modern processors and provide an interface to user-level processes to monitor their performance in terms of the number of micro-architectural events, executed during the process execution. In this paper, we analyze the leakage from these HPC events and present a new micro-architectural side-channel attack that observes the number of instruction counts during the execution of an encryption algorithm as side-channel information to recover the secret key. This paper explores the fact that the instruction counts can act as a side channel and then describes the instruction profiling attack (IPA) methodology with the help of two block ciphers, namely AES and CLEFIA, on Intel and AMD processors. We follow the principles of profiled instruction attacks and show that the proposed attack is more potent than the well-known cache timing attacks in literature. We also perform experiments on ciphers implemented with popular time fuzzing schemes to subvert timing attacks. Our results show that while the countermeasure successfully stops leakages through the timing channels, it is vulnerable to the instruction profiling attack. We validate our claims by detailed experiments on contemporary Intel and AMD platforms to demonstrate that seemingly benign instruction counts can serve as side channels even for block cipher implementations that are hardened against timing attacks. In addition to it, we present detailed experimentation to analyze the rationale behind the attack and also explore the performance of IPA on a countermeasure designed to subvert the cache-based attacks considering a case study on CLEFIA.

An empirical study of the effect of source-level loop transformations on compiler stability

Modern compiler optimization is a complex process that offers no guarantees to deliver the fastest, most efficient target code. For this reason, compilers struggle to produce a stable performance from versions of code that carry out the same computation and only differ in the order of operations. This instability makes compilers much less effective program optimization tools and often forces programmers to carry out a brute force search when tuning for performance. In this paper, we analyze the stability of the compilation process and the performance headroom of three widely used general purpose compilers: GCC, ICC, and Clang. For the study, we extracted over 1,000 <pre>for</pre> loop nests from well-known benchmarks, libraries, and real applications; then, we applied sequences of source-level loop transformations to these loop nests to create numerous semantically equivalent mutations ; finally, we analyzed the impact of transformations on code quality in terms of locality, dynamic instruction count, and vectorization. Our results show that, by applying source-to-source transformations and searching for the best vectorization setting, the percentage of loops sped up by at least 1.15x is 46.7% for GCC, 35.7% for ICC, and 46.5% for Clang, and on average the potential for performance improvement is estimated to be at least 23.7% for GCC, 18.1% for ICC, and 26.4% for Clang. Our stability analysis shows that, under our experimental setup, the average coefficient of variation of the execution time across all mutations is 18.2% for GCC, 19.5% for ICC, and 16.9% for Clang, and the highest coefficient of variation for a single loop nest reaches 118.9% for GCC, 124.3% for ICC, and 110.5% for Clang. We conclude that the evaluated compilers need further improvements to claim they have stable behavior.

Efficient Side-Channel Protections of ARX Ciphers

The current state of the art of Boolean masking for the modular addition operation in software has a very high performance overhead. Firstly, the instruction count is very high compared to a normal addition operation. Secondly, until recently, the entropy consumed by such protections was also quite high. Our paper significantly improves both aspects, by applying the Threshold Implementation (TI) methodology with two shares and by reusing internal values as randomness source in such a way that the uniformity is always preserved. Our approach performs considerably faster compared to the previously known masked addition and subtraction algorithms by Coron et al. and Biryukov et al. improving the state of the art by 36%, if we only consider the number of ARM assembly instructions. Furthermore, similar to the masked adder from Biryukov et al. we reduce the amount of randomness and only require one bit additional entroy per addition, which is a good trade-off for the improved performance. We applied our improved masked adder to ChaCha20, for which we provide two new first-order protected implementations and achieve a 36% improvement over the best published result for ChaCha20 using an ARM Cortex-M4 microprocessor.

Loop aware CFG matching strategy for accurate performance estimation in IR-level native simulation

Native simulation is a promising virtual prototyping candidate to accelerate design space exploration of hardware/software systems, early software developments and functional verification. However, it originally fails to provide non-functional information needed for software performance estimation. To add this capability, the general approach is to extract performance metrics from target binary code and back-annotate it in the high-level code from which the binary was generated. However, due to compiler optimizations, the high-level code and the binary code usually have different structures which makes software annotation a complex task. This work proposes a loop-based mapping scheme that reflects optimizations from the binary to the high-level IR for the purpose of precisely placing performance annotations in the software and yielding accurate performance estimates. Experiments on instruction count show in average around 2% of error while conserving a considerable speedup compared to instruction set simulation.

JPR

Java PathFinder (JPF) is a backtrackable Java Virtual Machine (JVM), which is implemented in Java and runs on a standard JVM (e.g., Oracle HotSpot). Thus, a JPF developer can use off-the- shelf Java debuggers (e.g., jdb) when debugging code that makes up JPF. JPF explores all non-deterministic executions of a given target program and monitors for property violations. To facilitate debugging of the target program, JPF can capture and replay the execution trace that leads to a property violation. While the deterministic replay is invaluable, the replay with JPF does not allow the developer to attach an off-the-shelf Java debugger to the target program (e.g., step through the application code, set breakpoints, etc.). We present a technique, dubbed JPR, to improve the debugging experience of the JPF captured traces by migrating the JPF traces to a new format that can be executed using the standard JVM. JPR annotates each JPF trace, during the capture phase, with ex- tra data (e.g., instruction index, instruction count, etc.); the an- notated trace is then used to instrument Java bytecode to enforce the same execution trace on a standard JVM. JPR is compatible with various optimizations, e.g., state matching and partial-order reduction. We evaluated JPR on all multi-threaded Java pro- grams in the official JPF distribution. Our results show that JPR successfully replayed all JPF traces on the standard JVM with reasonable overhead during both recording and replaying.

Control-theoretic adaptive cache-fair scheduling of chip multiprocessor systems

In chip multiprocessor scheduling, cache memory awareness is critical. However, most existing cache-aware multiprocessor scheduling methods are static and open-loop and thus do not work well in dynamic environments. To address this challenging problem, a control-theoretic approach is presented in this paper for adaptive cache-fair multiprocessor scheduling. The adaptive cache-fair multiprocessor scheduling uses process models to estimate the shared cache size requirements and the instruction count variations of the threads running on multiprocessor cores. Then, it feeds the estimated information back to an adaptive controller. Designed from the process models, the controller decides processor cycle re-allocation through model computation to maintain the instruction counts of the multiple threads at their desired values. The effectiveness of the adaptive cache-fair multiprocessor scheduling is demonstrated through examples.