Temporal characterization of memory access behaviors in SPEC CPU2017 workloads: Analysis and synthesis

Abstract

The SPEC CPU2017 benchmark suite has received wide attention in both academia and industry. However, few work have studied the memory behaviors in SPEC CPU2017 workloads from a time dependence perspective. We run all SPEC CPU2017 benchmarks and collect 43 memory traces. This paper examines the correlation of memory access intervals in all SPEC CPU2017 workloads. The results show that there is a certain degree of correlation in the majority of the SPEC CPU2017 applications (79%). This observation differs from the SPEC CPU2006 in which the correlation of access behavior only exists in a small number of applications (27%). This phenomenon may be associated with an order-of-magnitude increase in the average instruction count in SPEC CPU2017. For each of 34 SPEC CPU2017 workloads with a certain degree of correlation, this paper estimates the Hurst parameters to test the self-similar property statistically. All Hurst parameters estimated are greater than 0.5, confirming the existence of self-similarity in SPEC CPU2017 workloads. We further deploy a versatile memory trace generator based on the inputs measured from the collected SPEC CPU2017 trace data. Experimental results show that the proposed model is robust for the memory access synthesis of various SPEC CPU2017 applications, and can accurately characterize the burstiness of memory access behaviors in SPEC CPU2017 workloads and more faithful than conventional models.