Input Output Automata Research Articles

The groups 𝐺 satisfying a functional equation 𝑓(𝑥𝑘) = 𝑥𝑓(𝑥) for some 𝑘 ∈ 𝐺

Abstract We study the groups 𝐺 with the curious property that there exists an element k ∈ G k\in G and a function f : G → G f\colon G\to G such that f ⁢ ( x ⁢ k ) = x ⁢ f ⁢ ( x ) f(xk)=xf(x) holds for all x ∈ G x\in G . This property arose from the study of near-rings and input-output automata on groups. We call a group with this property a 𝐽-group. Finite 𝐽-groups must have odd order, and hence are solvable. We prove that every finite nilpotent group of odd order is a 𝐽-group if its nilpotency class 𝑐 satisfies c ⩽ 6 c\leqslant 6 . If 𝐺 is a finite 𝑝-group, with p > 2 p>2 and p 2 > 2 ⁢ c - 1 p^{2}>2c-1 , then we prove that 𝐺 is 𝐽-group. Finally, if p > 2 p>2 and 𝐺 is a regular 𝑝-group or, more generally, a power-closed one (i.e., in each section and for each m ⩾ 1 m\geqslant 1 , the subset of p m p^{m} -th powers is a subgroup), then we prove that 𝐺 is a 𝐽-group.

Verifying correctness of persistent concurrent data structures: a sound and complete method

Non-volatile memory (NVM), aka persistent memory, is a new memory paradigm that preserves its contents even after power loss. The expected ubiquity of NVM has stimulated interest in the design of persistentconcurrent data structures, together with associated notions of correctness. In this paper, we present a formal proof technique for durable linearizability, which is a correctness criterion that extends linearizability to handle crashes and recovery in the context ofNVM.Our proofs are based on refinement of Input/Output automata (IOA) representations of concurrent data structures. To this end, we develop a generic procedure for transforming any standard sequential data structure into a durable specification and prove that this transformation is both sound and complete. Since the durable specification only exhibits durably linearizable behaviours, it serves as the abstract specification in our refinement proof. We exemplify our technique on a recently proposed persistentmemory queue that builds on Michael and Scott’s lock-free queue. To support the proofs, we describe an automated translation procedure from code to IOA and a thread-local proof technique for verifying correctness of invariants.

Cryptographic Key Exchange Protocol with Message Authentication Codes (MAC) Using Finite State Machine

In this work, we explore the authentication and verification of key exchange protocol using Message Authentication Code (MAC). We propose a new MAC scheme model using input-output automata to protect the integrity of the secret key in the key exchange protocol. Our scheme was devised in reference to the Diffie-Hellman communication protocol model. We divided our MAC protocol into three stages of communication sequences in order to simplify the model and the design of automata machine. In the final result, we combined all stages and represented the protocol as Cryptographic MAC Protocol in the regular language. We have shown that the cryptographic MAC protocol for key exchange protocol can be implemented using finite input-output automata with some small modification of the finite state machine. The proposed protocol would be useful for implementation ina lightweight or a secure smart devicescommunication in the wireless sensor nodes (WSN) network.

Finite Bisimulation of Reactive Untimed Infinite State Systems Modeled as Automata With Variables

Some discrete-event systems such as software are typically infinite state systems, and a commonly used technique for performing formal analysis such as automated verification is based on their finite abstractions. In this paper, we consider a model for reactive untimed infinite state systems called input-output extended finite automaton (I/O-EFA), which is an automaton extended with discrete variables such as inputs, outputs, and data. Using I/O-EFA as a model many value-passing processes can be represented by finite graphs. We study the problem of finding a finite abstraction that is bisimilar to a given I/O-EFA. We present a sufficient condition under which the underlying transition system of an I/O-EFA admits a finite bisimilar quotient. We then identify a class of I/O-EFAs for which a partition satisfying our sufficient condition can be constructed by inspecting the structure of the given I/O-EFA. We also identify a lower bound abstraction (that is coarser than any finite bisimilar abstraction), and present an iterative refinement algorithm whose termination guarantees the existence of a finite bisimilar abstraction. The results are illustrated through examples that model reactive software.

The Modeling Procedures for Model-Based Diagnosis of Slowly Changing Fault in Hybrid System

Many traditional model-based diagnosis is based on the assumption of abrupt faults. This assumption can lead to a wrong result when the faults are slowly changing. The diagnosis of slowly changing faults can be considered to be an open area in controlling complex system of large scale. The slowly changing faults are difficult to detect, extremely when interlacing with abrupt faults. The modeling of diagnosis in slowly changing faults is different with abrupt faults. A modeling method of slowly changing faults on hybrid system is proposed, based on Hybrid Input Output Automata and mixture bond graph. The effectiveness is proved by method testing on three-tank system. The testing results provide a basic model to faults discovering and isolating

Robustness testing of composed real-time systems

In this paper, we suggest a methodology for testing robustness of Real-Time Component-Based Systems (RTCBS). A RTCBS system is described as a collection of components where each component is modeled as a Timed Input-Output Automaton (TIOA). For each component, we handle two specifications: a nominal one and a degraded one. We extract test sequences from the nominal specification and we inject automatically faults in order to model hostile environments. Then we present an adequate test architecture consisting of the System Under Test (SUT) of components, and a distributed tester that consists of a set of coordinating testers. Each tester is dedicated to test a single SUT component. A test execution algorithm is presented. Testing the SUT is divided into two phases. In the first phase, the tester executes the generated test sequences of each component in isolation and records the feedback of this experimentation. The robustness is checked by verifying if the recorded results are accepted by the degraded specification of each component. If all components are robust according to the inserted hazards, we check the robustness of communications between components respecting the same process described before.

Modeling of asynchronous discrete-event systems as networks of input-output automata

A new approach for component-oriented modeling of asynchronous discrete-event systems is presented where input-output (I/O) automata are used for representing the components. Coupling signals are introduced to describe the interactions among the components. The resulting network of I/O-automata has a direct correspondence to the block diagram. By using the parallel composition rule known from standard automata modeling as an example, it is shown that the new model is applicable for at least the same class of asynchronous discrete-event systems as the known modeling formalisms.

Integrating formal verification and conformance testing for reactive systems

In this paper, we describe a methodology integrating verification and conformance testing. A specification of a system - an extended input-output automaton, which may be infinite-state - and a set of safety properties (nothing bad ever happens) and possibility properties (something good may happen) are assumed. The properties are first tentatively verified on the specification using automatic techniques based on approximated state-space exploration, which are sound, but, as a price to pay for automation, are not complete for the given class of properties. Because of this incompleteness and of state-space explosion, the verification may not succeed in proving or disproving the properties. However, even if verification did not succeed, the testing phase can proceed and provide useful information about the implementation. Test cases are automatically and symbolically generated from the specification and the properties and are executed on a black-box implementation of the system. The test execution may detect violations of conformance between implementation and specification; in addition, it may detect violation/satisfaction of the properties by the implementation and by the specification. In this sense, testing completes verification. The approach is illustrated on simple examples and on a bounded retransmission protocol.

Verifying Concurrent Data Structures by Simulation

We describe an approach to verifying concurrent data structures based on simulation between two Input/Output Automata (IOAs), modelling the specification and the implementation. We explain how we used this approach in mechanically verifying a simple lock-free stack implementation using forward simulation, and briefly discuss our experience in verifying three other lock-free algorithms which all required the use of backward simulation.

Timed Wp-method: testing real-time systems

Real-time systems interact with their environment using time constrained input/output signals. Examples of real-time systems include patient monitoring systems, air traffic control systems, and telecommunication systems. For such systems, a functional misbehavior or a deviation from the specified time constraints may have catastrophic consequences. Therefore, ensuring the correctness of real-time systems becomes necessary. Two different techniques are usually used to cope with the correctness of a software system prior to its deployment, namely, verification and testing. In this paper, we address the issue of testing real-time software systems specified as a timed input output automaton (TIOA). TIOA is a variant of timed automaton. We introduce the syntax and semantics of TIOA. We present the potential faults that can be encountered in a timed system implementation. We study these different faults based on TIOA model and look at their effects on the execution of the system using the region graph. We present a method for generating timed test cases. This method is based on a state characterization technique and consists of the following three steps: First, we sample the region graph using a suitable granularity, in order to construct a subautomaton easily testable, called grid automaton. Then, we transform the grid automaton into a nondeterministic timed finite state machine (NTFSM). Finally, we adapt the generalized Wp-method to generate timed test cases from NTFSM. We assess the fault coverage of our test cases generation method and prove its ability to detect all the possible faults. Throughout the paper, we use examples to illustrate the various concepts and techniques used in our approach.

A DEADLOCK RESOLUTION ALGORITHM

In this paper we consider the problem of the distributed deadlock resolu­ tion. Starting from a high level specification of the problem and the resolution algorithm for a system with single request model, we provide successive levels of decreasing ab­ straction of the initial specification in order to achieve a solution in a complete distributed system. The successive refinements and the final distributed deadlock resolution algo­ rithm are formaly described and proved by using the Input-Output Automata Model. The proposed solution is a modification of the algorithms in Mitchell and Merritt (1984) and Gonzalez de Mendivil et al. (1993) and preserves a similar message traffic to resolve a deadlock.

Behaviorism, finite automata, and stimulus response theory

In this paper it is argued that certain stimulus-response learning models which are adequate to represent finite automata (acceptors) are not adequate to represent noninitial state input-output automata (transducers). This circumstance suggests the question whether or not the behavior of animals if satisfactorily modelled by automata is predictive. It is argued in partial answer that there are automata which can be explained in the sense that their transition and output functions can be described (roughly, Hempel-type covering law explanation) while their behaviors are in principle not predictable short of possession of their complete histories or of information concerning present internal states by indirect observation.