Size Of Input Vector Research Articles

Conditional generative adversarial network for generation of three-dimensional porous structure of solid oxide fuel cell anodes with controlled volume fractions

A structure generation model based on a generative adversarial network (GAN) is developed to synthesize artificial porous microstructures of solid oxide fuel cell (SOFC) anodes. Different from the conventional framework of GANs, additional training is performed for the generator to control statistical parameters, namely, volume fractions, of the generated structures. The developed model is validated by comparing the synthesized structures with the real electrode microstructures obtained by three-dimensional microscopy analysis. Microstructural parameters, such as volume fraction, specific surface area, and triple-phase boundary density, are used for the comparison in addition to the visual observation. The effect of the input vector size for the generator and the definition of the loss on the ability to generate realistic structures and control the volume fractions of the structures is investigated. The developed model successfully generates realistic anode microstructures with accurately controlled volume fractions, even for compositions not included in the training datasets. It is also found that the balance between the losses influences the accuracy of the volume fraction control and diversity of the generated structures. The GAN model developed is expected to be helpful in constructing a digital twin of electrode fabrication and evaluation processes.

Performance Assessment of Joint Optical-Digital Nonlinearity Mitigation Schemes in Long-Haul Systems

The combined approach of optical and digital nonlinearity mitigation techniques have been shown to have an edge over the individual schemes, tackling their drawbacks and improving compensation capabilities. We demonstrated fiber-nonlinearity mitigation of 32 GBd single-polarization 16QAM signals transmitted over an 800-km dispersion-managed link using optical phase conjugation (OPC) and digital-domain neural networks (NN). Our implemented NN comprised a recurrent neural network (RNN), and a reservoir computing network (RCN). To further compensate for the penalty introduced by the design of OPC, we employed NN schemes in the digital signal processing and applied it to the signal after transmission in the OPC-assisted link. We present the results for optimizing the NN models for important hyper-parameters like the number of hidden layer neurons and the input vector size. The proposed joint approach achieves Q <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> -factor improvements up to 1.8 dB while surpassing the improvements of the individual schemes. Our experiments indicate that the joint approach has the potential to reduce the overall complexity of NN architectures in terms of the size of the hidden layer and input vector.

LSTM-CNN model of drowsiness detection from multiple consciousness states acquired by EEG

This study aimed to design a deep neural network for electroencephalography (EEG)-based drowsiness detection in multiple consciousness states, i.e., “awake,” “sleep,” and “drowsiness.” Few studies have seriously considered the optimal input vector size or labeling method in classifying multiple consciousness states, which may affect classification performance. To determine the optimal input vector length, i.e., window length, three neural network models (long short-term memory [LSTM], convolutional neural network [CNN], and combined LSTM and CNN) and four feature-based models were tested with six different levels of window length. The EEG dataset was acquired from 19 participants with randomly assigned auditory stimuli and button responses. The EEG data were labeled into three classes (awake, sleep, and drowsiness) based on the defined button response pattern corresponding to the stimuli. The results demonstrated that when the input vector size exceeded 8 sec, the performance of the neural network models dropped rapidly; however, when the window size was less than 8 sec, the performance change according to the window size was small. In contrast, the performance of feature-based models increased continuously as the window size increased. The LSTM model yielded the best accuracy (86%) for a 1 sec window length, and the LSTM-CNN model yielded the best kappa index (0.77) for a 4 sec window length. In addition, the proposed model was applied to the binary classification of normal consciousness (awake) and low consciousness (drowsiness and sleep) states to determine whether this model works appropriately in actual applications such as drowsiness detection in a driving environment. For binary classification, the LSTM-CNN model resulted in 0.95 F1 scores in 4000-ms. When a short input data (500 msec) is used, the LSTM-CNN model resulted in an average accuracy of 85.6% and a kappa index of 0.77 for the three-class classification problem and 0.94 F1 scores for the binary classification problem. In conclusion, we demonstrated that the proposed model could effectively detect drowsiness. Furthermore, a significant correlation was found between reaction time and drowsiness. However, using the reaction time as an index for labeling drowsiness was challenging because of the high false-negative ratio.

SRIF: Scalable and Reliable Integrate and Fire Circuit ADC for Memristor-Based CIM Architectures

Emerging computation-in-memory (CIM) paradigm offers processing and storage of data at the same physical location, thus alleviating critical memory-processor communication bottlenecks suffered by conventional von-Neumann architecture. Storage of data in a CIM architecture is analog in nature and therefore computation is performed in analog domain i.e. inputs and outputs are analog values. Since the outside computing environment is digital, analog-to-digital converters (ADC) are utilized to perform the output data conversion. However, ADC designs are bulky, power-hungry circuits that are prone to design variations and therefore, play an important role in determining the computing efficiency of CIM architectures. In this paper, we present a scalable and reliable integrate and fire circuit ADC (SRIF-ADC) design for CIM architectures, suitable for stringent power and area constraints. We devise a technique to stabilize the node receiving analog inputs that allows more rows to be activated at the same time, thereby increasing the operand size of input vectors. This allows better scalability in terms of higher parallelism of operations. We employ a self-timed variation-aware design approach and design measures to drastically reduce read disturb of memristor devices that address reliability issues related to the ADC design. In addition, we present a compact, built-in sample-and-hold circuit to replace the large-sized capacitance and built-in weighting technique to alleviate the need for post-processing. For multiply-and-accumulate (MAC) operation, our simulation results show that we can improve the computational parallelism by 3X as well as ADC conversion speed and energy efficiency are improved by 2X and 11.6X, respectively, compared to the state-of-the-art design.

Power quality disturbance classification based on efficient adaptive Arrhenius artificial bee colony feature selection

Automatic power quality disturbance (PQD) classification is a challenging task for industry and utility. This work presents an algorithm for classifying the PQDs based on the combination of novel feature selection with machine learning (ML) techniques. In this work, discrete wavelet transform (DWT) is utilized to decompose the PQD signals and hence minimize the size of input vectors with multi-resolution analysis. Novel optimal feature selection-based classification is performed using probabilistic neural network and adaptive Arrhenius artificial bee colony (PNN- adaptive AABC) algorithm. The selection of optimal features may discard the redundant features and retain the useful features. Also, this adaptive AABC algorithm provides a higher convergence rate, and this is used for accurate feature selection since this work is applied for 16 PQD events. In other case, features extracted with DWT are processed and trained with various ML algorithms such as Decision Tree, support vector machine (SVM), and K-nearest neighbor (KNN). Finally, the comparison accuracy of the proposed classifier is compared with the existing classifiers. The proposed technique found to give improved results in most of the cases like accuracy, prediction speed, and training time, and the outcomes acquired as 99.98%, ~1260 obs/seconds, and 13.113 seconds, respectively.

Vibration Response-Based Intelligent Non-Contact Fault Diagnosis of Bearings

Abstract Accelerometers, used as vibration pickups in machine health monitoring systems, need physical connection to the machine tool through cables, complicating physical systems. A non-contact laser based vibration sensor has been developed and used for bearing health monitoring in this article. The vibration data have been acquired under speed and load variation. Hilbert transform (HT) has been applied for denoising the vibration signal. An extraction of condition monitoring indicators from both raw and envelope signals has been made, and the dimensionality of these extracted indicators was deducted with principal component analysis (PCA). Sequential floating forward selection (SFFS) method has been implemented for ranking the selected indicators in order of significance for reduction in the input vector size and for finalizing the most optimal indicator set. Finally, the selected indicators are passed to k-nearest neighbor (kNN) and weighted kNN (WkNN) for diagnosing the bearing defects. The comparative analysis of the effectiveness of kNN and WkNN has been executed. It is evident from the experimental results that the vibration signals obtained from developed non-contact sensor compare adequately with the accelerometer data obtained under similar conditions. The performance of WkNN has been found to be slower compared to kNN. The proposed fault detection methodology compares very well with the other reported methods in the literature. The non-contact fault detection methodology has an enormous potential for automatic recognition of defects in the machine, which can provide early signals to avoid catastrophic failure and unplanned equipment shutdowns.

Efficient Fixed-Width Adder-Tree Design

Conventionally, fixed-width adder-tree (AT) design is obtained from the full-width AT design by employing direct or post-truncation. In direct-truncation , one lower order bit of each adder output of full-width AT is post-truncated, and in the case of post-truncation , { ${p}$ } lower order-bits of final-stage adder output are truncated, where ${p}={{\lceil }{\log }_{{2}}{N}{\rceil }}$ and ${N}$ is the input-vector size. Both these methods does not provide an efficient design. In this brief, a novel scheme is presented to obtain fixed-width AT design using truncated input. A bias estimation formula based on probabilistic approach is presented to compensate for the truncation error. The proposed fixed-width AT design for input-vector sizes 8 and 16 offers (37%, 23%, 22%) and (51%, 30%, 27%) area-delay product saving for word-length sizes (8, 12, 16), respectively, and calculates the output almost with the same accuracy as the post-truncated fixed-width AT, which has the highest accuracy among the existing fixed-width AT. Further, we observed that Walsh–Hadamard transform based on the proposed fixed-width AT design reconstruct higher-texture images with higher peak signal-to-noise ratio (PSNR) and moderate-texture images with almost the same PSNR compared to those obtained using the existing AT designs. Besides, the proposed design creates an additional advantage to optimize other blocks appear at the upstream of the AT in a complex design.

Improved Homomorphic Discrete Fourier Transforms and FHE Bootstrapping

Homomorphic encryption (HE), which enables computation on ciphertexts without any leakage, rise as a most promising solution for privacy-preserving data processing, including secure machine learning and secure out-sourcing computation. Despite the extensive applicability of HE, the current constructions are sometimes considered as impractical due to its inefficiency. In this paper, we propose improvements on the linear transformation in bootstrapping, a technique allowing the infinite number of operation for HE, and homomorphic discrete Fourier transformation (DFT) using batch homomorphic encryption. We observe that the multiplication of a sparse diagonal matrix and ciphertext of a vector can be done within O(1) homomorphic computations. This observation induces the faster algorithm for linear transformation in bootstrapping and homomorphic DFT. To achieve this, we use Cooley-Tukey matrix factorization and construct a new recursive factorization of the linear transformation in bootstrapping. Our method with radix r only requires O(r log r n) constant vector multiplication and O(√r log r n) rotations by consuming O(log r n) depth when the input vector size is n. The previous method used in the library, a library that implements homomorphic encryption for approximate computation, requires O(n) and O(√n), respectively. To show the performance improvement, we implement our method on top of the library. Our implementation, along with further few techniques, of these algorithms show the significant improvements compared to the previous algorithm. New homomorphic DFT with length 2 14 only takes about 8s which results 150 times faster than the previous method. Furthermore, the bootstrapping takes about 2 minutes for ℂ 32768 plaintext space with 8-bit precision, which takes 26 hours with same bit precision using the previous method.

Robust and Large-Scale Convolution through Stochastic-Based Processing without Multipliers

Large-scale discrete convolution, well-known to be computationally intensive, is a fundamental algorithmic building block in many computer vision and artificial intelligence applications. This work presents a novel stochastic-based hardware architecture and design that computes discrete convolution based on the widely-used convolution theorem. Our approach has three advantages. First, it can achieve approximately <inline-formula><tex-math notation="LaTeX">${\mathrm O} (1)$</tex-math></inline-formula> in algorithmic complexity for any given absolute error bound <inline-formula><tex-math notation="LaTeX">$d$</tex-math></inline-formula> and any given input vector size <inline-formula><tex-math notation="LaTeX">$N$</tex-math></inline-formula> . This computing complexity, when compared with <inline-formula><tex-math notation="LaTeX">${\mathrm O} (N^2)$</tex-math></inline-formula> and <inline-formula><tex-math notation="LaTeX">${\mathrm O} (N \log N)$</tex-math></inline-formula> operations for conventional multiplier-based and FFT-based architectures respectively, represents a significant improvement, although at the cost of degraded computing accuracy. Second, to achieve a given computing accuracy, our proposed stochastic-based convolution can be analytically proven to only require a moderate number of random samples, e.g., 788 random samples can achieve 95 percent accuracy at 99 percent confidence level for a convolution with <inline-formula><tex-math notation="LaTeX">$N=128$</tex-math></inline-formula> . Third, this proposed stochastic-based architecture is highly fault-tolerant because the information to be processed is encoded with a large ensemble of random samples. As such, the local perturbations of its computing accuracy will be dissipated globally, thus becoming inconsequential to the final overall results. We believe that, being highly scalable and energy efficient, our stochastic-based convolution architecture is well-suited for many real-time embedded applications, especially those perception-based computing tasks that are inherently fault-tolerant. In short, this work provides an elegant way to tradeoff between computing accuracy and computing performance/hardware efficiency for many real-world convolution-based applications.

Novel Data-Access Scheme and Efficient Parallel Architecture for Multi-level Lifting 2-D DWT

Data-access scheme affects the complexity of parallel architectures performing computation of multi-level two-dimensional (2-D) discrete wavelet transform (DWT). In this paper, we made a study on the data-access schemes considered in the existing parallel 2-D DWT architectures. Based on this study, a novel data-access scheme is proposed to avoid data multiplexing, which is common in the existing parallel architectures. Further, a block formulation is presented for vector computation of multi-level lifting 2-D DWT. A generic design of processing unit for computing one-level 2-D DWT is derived using the proposed block formulation. The proposed generic design resizes by a single parameter, i.e., the input-vector size. A regular and modular parallel architecture is derived using the generic processing unit design. The proposed parallel architecture easily scalable for higher block sizes as well as higher DWT levels without sacrificing its circuit regularity and modularity. This is an important feature of the proposed architecture. Comparison result shows that the proposed architecture for three-level DWT and block size 64 offers a saving in 24% area–delay–product (ADP) and 10% power consumption, and higher saving for higher block sizes than the best available similar structure without any overhead memory unlike the existing structure.

서베일런스 네트워크에서 패턴인식 기반의 실시간 객체 추적 알고리즘

This paper proposes algorithm to reduce the computing time in a neural network that reduces transmission of data for tracking mobile objects in surveillance networks in terms of detection and communication load. Object Detection can be defined as follows : Given image sequence, which can forom a digitalized image, the goal of object detection is to determine whether or not there is any object in the image, and if present, returns its location, direction, size, and so on. But object in an given image is considerably difficult because location, size, light conditions, obstacle and so on change the overall appearance of objects, thereby making it difficult to detect them rapidly and exactly. Therefore, this paper proposes fast and exact object detection which overcomes some restrictions by using neural network. Proposed system can be object detection irrelevant to obstacle, background and pose rapidly. And neural network calculation time is decreased by reducing input vector size of neural network. Principle Component Analysis can reduce the dimension of data. In the video input in real time from a CCTV was experimented and in case of color segment, the result shows different success rate depending on camera settings. Experimental results show proposed method attains 30% higher recognition performance than the conventional method.

A Novel Change Detection Method Using Independent Component Analysis and Oriented-Object Method

hrough analyzing problems brought on change detection methods of high-resolution remote sensing images, a novel change detection algorithm is proposed. First, feature images of image’s objects extracted using oriented-object method serve as data of input vector to estimate sub-space for Independent Component Analysis(ICA), which can improve effect of noise suppression, simultaneously, a new algorithm using self-adapted weight is proposed in order to extract image’s object, which optimizes processing method on oriented-object deeply；new partitioning scheme using undecimated discrete wavelet transform(UDWT) overcomes effectively prominent problem which shrinking of the size of input vector becomes leads to unprecisely estimation of sub-space for ICA. Compared with typical algorithm, such as ICA and UDWT, simulation results show that new algorithm improves robust and veracity of change detection for high-resolution images greatly.

A simple interpolating algorithm for the rapid and accurate calculation of the Voigt function

A simple interpolating algorithm for rapid calculation of the Voigt function with high accuracy is presented. It can utilize any existing rapid algorithm as a subprogram for the pre-computation of the selected points. Such approach is particularly efficient for massive input arrays and, compared to the Wells algorithm, accelerates the computation, improves the accuracy, and increases the input vector size by factors greater than 35, 7, and 10, respectively. The calculated results were compared with exponential and arctangent expansion approximations of the Voigt function. It is found that the relative error in the Wells algorithm slightly exceeds the supposed accuracy of 10 −5.

A Fast VQ Codebook Generation Algorithm Based on Otsu Histogram Threshold

In vector quantization, the codebook generation problem can be formulated as a classification problem of dividing N $_{p}$ training vectors into N $_{c}$ clusters, where N $_{p}$ is the training size of input vectors and N $_{c}$ is the codeword size of codebook. For large N $_{p}$ and N $_{c}$ , a traditional search algorithmsuch as the LBG method can hardly find the global optimal classification and needs a great deal of calculation. In this paper, a novel VQ codebook generation method based on Otsu histogram threshold is proposed. The computational complexity of squared Euclidean distance can be reduced to O(N $_{p}$ log $_{2}$ N $_{c}$ ) for a codebook with gray levels. Our method provides better image quality than recent proposed schemes in high compression ratio. The experimental results and the comparisons show that this method can not only reduce the computational complexity of squared Euclidean distance but also find better codewords to improve the quality of the resulted VQ codebook.

Neural-Network Application for Mechanical Variables Estimation of a Two-Mass Drive System

This paper deals with the application of neural networks (NNs) to the mechanical state estimation of the drive system with elastic joint. The torsional vibrations of the two-mass system are damped using the control structure with additional feedbacks from the torsional torque and the load-side speed. These feedbacks signals are obtained using NN estimators. The learning procedure of the NNs is described, and the influence of the input vector size to the accuracy of the state-variable estimation is investigated. The neural estimators of the torsional torque and the load machine speed are tested with open-loop and closed-loop control structures. The simulation results are confirmed by laboratory experiments

Forecasting runoff coefficients using ANN for water resources management: The case of Notwane catchment in Eastern Botswana

Forecasting future response behaviour of a semi-arid catchment in terms of runoff coefficient being trivial, an attempt has been made to apply an artificial neural network (ANN) model to forecast the runoff coefficients (ROC) for the rapidly urbanizing Notwane catchment system in Botswana. Runoff coefficients computed from 1978 to 2000, by the water balance technique have been used to develop the optimal network architecture with appropriate choice of the size of input vectors, number of hidden layers and number of neurons in the hidden layers, training algorithms and transfer functions for the network. The developed network has then been used to simulate the runoff coefficients for the above period. Based on its performance in terms of reproducibility of the water balance runoff coefficients, the network was used to forecast the runoff coefficients up to 2020 and it was found that the increase in runoff coefficients is about 1% per year. Based on the weights given by the network to the input variables, it was found that while about 48% contribution came from climatic factors, 52% came from the land use/land cover.

Estimation of chemical oxygen demand by ultraviolet spectroscopic profiling and artificial neural networks

A simple method based on the mathematical treatment of spectral absorbance profiles in conjunction with artificial neural networks (ANNs) is demonstrated for rapidly estimating chemical oxygen demand (COD) values of wastewater samples. In order to improve spectroscopic analysis and ANN training time as well as to reduce the storage space of the trained ANN algorithm, it is necessary to decrease the ANN input vector size by extracting unique characteristics from the raw input pattern. Key features from the spectral absorbance pattern were therefore selected to obtain the spectral absorbance profile, reducing the ANN input vector from 160 to 10 selected inputs. The results indicate that the COD values obtained from the selected absorbance profiles agreed well with those obtained from the entire absorbance pattern. The spectral absorbance profile technique was also compared to COD values estimated by a multiple linear regression (MLR) model to validate whether ANNs were better and more robust models for rapid COD analysis. It was found that the ANN model predicted COD values closer to standard COD values than the MLR model.

A unified systolic array design for kernel functions of video compression

In video compression, some kernel functions such as block matching, discrete wavelet transform, vector quantization, etc., are of prime essential, but with a large amount of computation. Recently, many systolic array architectures have been designated for performing each of those functions in real time. In fact, many kernel functions contain the similar computational procedure. If we dissect these functions into the basic matrix-vector product forms, a unified design for them becomes feasible. In this brief, by carefully extracting the common computation component, a unified one-dimensional systolic array design that can perform at least the above three functions is presented. In this design, the input data is serial-in to save the amount of pins required, and the data flow are carefully arranged to simplify the interconnection between computation components. When 64 registers are in the on-chip memory, our design can perform three typical functions: (1) the full-search block matching with block size 16/spl times/16 and the search range (-8,7); (2) the 2-D Harr transform with block size 8/spl times/8; and (3) the vector quantization with input vector size 4/spl times/4 and codebook size 256. Since the unified architecture reduces hardware costs, and has a regular hardware structure, it is suited for VLSI implementation for video/image compression applications that require all the functions.