Input Reference Noise Research Articles

A 0.6V 119 dB High-CMRR Low-NEF PGA with common-mode voltage control for ECG recording

This paper proposes a programmable gain amplifier (PGA) with common-mode voltage control for ECG recording. In order to ensure that input common-mode interference (CMI) does not deteriorate amplifier performance, a novel common-mode voltage control module is proposed, which soaks up CMI and maintains the common-mode input within the expected range. Utilizing a standard 65 nm CMOS process, our PGA runs on a 0.6 V supply. This amplifier has a frequency response range of 10 Hz–57.0 kHz, a gain range of 0 dB–24 dB, and a noise efficiency factor (NEF) of 4.17. Its common-mode rejection ratio (CMRR) is over 119.2 dB, and input reference noise within the amplifier bandwidth is 6.6 μVrms.

The Design of a Low-Noise, High-Speed Readout-Integrated Circuit for Infrared Focal Plane Arrays

This paper describes the design of a low-noise, high-speed readout-integrated circuit for use in InGaAs infrared focal plane arrays, and analyzes the working principle and noise index of the pixel circuit in detail. The design fully considers the dynamic range, noise, and power consumption of the pixel circuit in which a capacitance transimpedance amplifier structure is adopted as the input stage circuit, and chip fabrication via an XFAB 0.18 µm CMOS process is successfully realized. The ROIC adopts monolithic integration and implements various functions, such as windowing, subsampling, and different integration and readout modes. The ROIC reached an array scale of 32 × 32, a frame rate of 100 Hz, and a readout rate of 20 Mbps with an analog power consumption of less than 52 mW. The measurement results show that the input reference noise can be reduced to 143 e- via the CDS, and the fully customized scheme has certain advantages in the research of high-performance ROICs.

Current state and challenges of ECG amplifiers

This paper describes and compares three amplifiers for ECG recording, namely a four-transistor stage band-pass amplifier, a DDA-based fully differential CMOS instrumentation amplifier and an OTA amplifier using current reuse. The performance metrics of the three amplifiers are listed, their respective advantages are compared, what factors limit their disadvantages are analyzed, the current state of the art and the direction of development of the ECG amplifier are indicated, and suggestions are given for further enhancement of the ECG amp. These amplifier circuits are designed in 0.35 µm CMOS and are verified by layout followed by simulation simulations. The results show that running at 2V dc supply, the quad-transistor stage amplifier and the DDA fully differential amplifier consume 672nW, obtain at least 2uVrms of input reference noise, and obtain greater common mode rejection ratios of 86dB and 83dB, while the OTA amplifier consumes less 320nW, obtains the most 2.05uVrms of input reference noise, and obtains a smaller common-mode rejection ratio of 65dB.

A 146-dB-Ohm Gain 14-pARMS Noise Patch-Clamp Amplifier for Whole-Cell Ion Current Detection

The membrane clamp technique is an important tool to reflect the electrophysiological characteristics of cells by recording the ionic currents of cellular channels. Embedded systems work in systems designed for specific user groups and are used to implement specific functions. The membrane clamp amplifier built with embedded technology has the advantages of miniaturization, specialization, low power consumption, high integration, high resource utilization, and a long life cycle, which can avoid the inconvenience to developers and experimenters due to the update of general-purpose computer software and hardware. In this paper, a patch-clamp amplifier (PCA) based on a transimpedance amplifier (TIA) is proposed, which includes a glass microelectrode series resistance/capacitance compensation circuit and feedback resistor parasitic capacitance compensation. The prototype is designed using 180 nm CMOS technology and occupies an area of 720 μ m × 630 μ m . The prototype achieves a transimpedance gain of 145.6 dB-Ohm, a -3 dB bandwidth greater than 15 kHz, and an input reference noise current of 13.98 pARMS. Experimental results show that the proposed PCA is capable of compensating up to 30 pF of electrode capacitance and up to 10 MΩ for 86% of the series resistance, respectively. In addition, when the feedback resistor parasitic capacitance compensation circuit is enabled, the overshoot phenomenon disappears, overcoming the shortcomings of the conventional diaphragm clamp amplifier current clamp and maintaining the original key performance.

A 4-μW Analog Front End Achieving 2.4 NEF for Long-Term ECG Monitoring.

An ultra-low-power low-noise analog front end (AFE) is presented in this work, aiming for long-term ECG with clear P-waves for clinical diagnose. The chopper amplifier with passive noise filter and PWM based offset cancellation results in an input-reference noise of 0.39 μVrms, which shows 3.7X noise improvements among the state-of-the-art designs. With the digital offset cancellation by the pulse-width modulation wave, the AFE achieves a low input-referred dc offset of 0.4 μV among 9 tested chips and a low drift under 30 μV. A dynamic scale ADC with low-power comparator strategy prevents the instability and signal-loss, achieving an SFDR of 71.6 dB. The proposed AFE achieves a noise-efficient-factor (NEF) of 2.4 with a power consumption of 4 μW. The fabricated chip is demonstrated in a miniature prototype for long-term ECG monitoring application, presenting a clear ECG waveform with visible P-wave. The simultaneously ECG recording with a medical grade 12-lead ECG Holter shows the effective acquisition of the prototype, proofing the better noise performance.

A design of readout IC with capacitively-coupled chopper current-feedback instrumentation amplifier in a 0.18 μm CMOS process

This paper describes a readout IC (ROIC), which consists of a capacitively coupled instrumentation amplifier (CCIA) and a discrete-time delta–sigma modulator. An active high-pass filter is embedded in the ripple reduction loop to suppress the noise ripple amplitude due to chop modulation. To accommodate the input with large electrode offset, dc-servo loop (DSL) and a 6 bit capacitive DAC are employed to suppress large electrode offset, while a positive feedback loop to boost its input impedance. The complete CCIA is implemented in a standard 0.18 μm 1P6M CMOS process. It occupies an area of 0.56 mm2 (including DSL) and consumes 52 μA current from a 3.3 V supply voltage. Measurement results indicate that the input reference noise PSD is 53.8 nV√Hz.

A Battery-Less Portable ECG Monitoring System With Wired Audio Transmission.

This paper proposes a batteryless electrocardiogram (ECG) monitoring chip and intelligent system with wired audio transmission, which can be applied to long-term and real-time ECG monitoring. The ECG signal is modulated and amplified in the front-end chip and then is transmitted through the microphone channel of the 3.5-mm headphone cable. The sinusoidal signals from the left and right channels are converted into a dc supply and a precise local oscillator signal in the front-end chip, respectively. The proposed system samples the signal through the high-precision audio analog-to-digital converter in smart devices and processes it through the internal software. Therefore, no external battery, local oscillator, and complicate modules are required in this system. A chopper/amplitude modulation (AM) reused mixer amplifier is proposed, which combines chopping with AM and reuses the local oscillator signal. The closed-loop gain of the proposed amplifier varies between 20 and 47 dB and can be automatically adjusted according to the amplitude of the output signal. The proposed chip was implemented in a standard 0.18-μm CMOS process and occupies 1.07 × 0.95 mm2 of core area. The power management module outputs a 1.5-V dc voltage to power the system. When connected with the headphone cable load, the chip consumes a total power of 156 μW. The proposed monitoring system has been verified by the audio device and MATLAB in the PC. The test results show that the input reference noise of the demodulated signal is 2.12 μVrms (0.1-200Hz) and the total harmonic distortion is 0.56%@3 mV input.

Full-Differential Folded-Cascode Front-End Receiver Amplifier Integrated Circuit for Capacitive Micromachined Ultrasonic Transducers.

This paper describes the design of a front-end receiver amplifier for capacitive micromachined ultrasonic transducer (CMUT). The proposed operational amplifier (op amp) consists of a full differential folded-cascode amplifier stage followed by a class AB output stage. A feedback resistor is applied between the input and the output of the op amp to make a transimpedance amplifier. We analyzed the equivalent circuit model of the CMUT element operating in the receiving mode and obtained the static output impedance and center frequency characteristics of the CMUT. The op amp gain, bandwidth, noise, and power consumption trade-offs are discussed in detail. The amplifier was fabricated using GlobalFoundries 0.18-μm complementary metal-oxide-semiconductor (CMOS) technology. The open loop gain of the amplifier is approximately 65 dB, and its gain bandwidth product is approximately 29.5 MHz. The measured input reference noise current was 56 nA/√Hz@3 MHz. The amplifier chip area is 325 μm × 150 μm and the op amp is powered by ±3.3 V, the static power consumption is 11 mW. We verified the correct operation of our amplifier with CMUT and echo-pulse shown that the CMUT center frequency is 3 MHz with 92% fractional bandwidth.

HIGH INDUCTANCE COIL EMBEDDED ON MAGNETIC SENSOR CHIP FOR BIOMAGNETIC SIGNAL MEASUREMENTS

For the purpose of biomagnetic measurements, a magnetic sensor chip is manufactured using a 0.18 μm complementary metal–oxide–semiconductor (CMOS) process. A high-inductance coil and an instrumentation amplifier (IA) are embedded on this chip. The embedded high-inductance coil sensor contains suitable sensitivity and bandwidth for biomagnetic measurements, and is designed via electromagnetic field simulation. A low-gm operational transconductance amplifier (OTA) is also implemented on the chip to reduce the transconductance value. The output signal sensitivity of the magnetic sensor chip is 3.25 fT/μV, and the output reference noise is [Formula: see text]. The instrumentation amplifier is designed to minimize the magnetic signal noise using current feedback and a band-pass filter (BPF) with a bandwidth between 0.5 kHz and 5 kHz. The common-mode rejection ratio (CMRR) is measured at 117.5 dB by the Multi-Project Chip test. The proposed magnetic sensor chip is designed such that the input reference noise is maintained below 0.87 μV.

Removal of ECG interference from surface respiratory electromyography

The signal to noise ratio (SNR) of surface respiratory electromyography signal is very low. Indeed EMG signal is contaminated by different types of noise especially the cardiac artefact ECG. This article explores the problem of removing ECG artefact from respiratory EMG signal. The new method uses an adaptive structure with an electrocardyographic ECG reference signal carried out by wavelet decomposition. The proposed algorithm requires only one channel to both estimating the adaptive filter input reference noise and the respiratory EMG signal. This new technique demonstrates how two steps will be combined: the first step decomposes the signal with forward discrete wavelet transform into sub-bands to get the wavelet coefficients. Then, an improved soft thresholding function was applied. And the ECG input reference signal is reconstructed with the transformed coefficients whereas, the second uses an adaptive filter especially the LMS one to remove the ECG signal. After trying statistical as well as mathematical analysis, the complete investigation ensures that all details and steps make proof that our rigorous method is appropriate. Compared to the results obtained using previous techniques, the results achieved using the new algorithm show a significant improvement in the efficiency of the ECG rejection.

Power line interference rejection from surface electromyography signal using an adaptive algorithm

This work focuses on the power line interference (PLI) rejection from surface EMG signal. It contains three parts: the algorithm, the experimental setting and the results. This study begins with describing the new technique, which consists in filtering respiratory surface electromyogram signals (EMG + PLI), then, becoming familiar with it. The proposed algorithm requires only one channel to both estimating the adaptive filter input reference noise and the EMG signal. The algorithm of PLI rejection has been organized into two steps. The first step insists to apply adaptive filter, especially the LMS one, in which the reference input is mathematically constructed using two different cosine functions; 50 Hz (the fundamental) function and 150 Hz (the first harmonic) function. Whereas, the second step applies the matching pursuit algorithm that uses the cosine packet dictionary to improve the result of PLI obtained at the first step. After trying statistical, as well as mathematical analysis, the complete investigation ensures that all details and steps make proof that our rigorous method is appropriate, we have also compared our method with the previous known techniques.

A linear model based noise evaluation of a capacitive servo-accelerometer fabricated by MEMS

The noise characterization of a capacitive servo-accelerometer using a linear model is presented in this paper. The input reference noise of electronic circuit is expressed as a capacitive variation and it is introduced to a linear model for frequency response, separately with the thermal mechanical noise. The simulated noise was generally found to conform to the measured noise in the experiment, suggesting that the model can be effectively used for noise evaluation of accelerometers fabricated in a similar fashion.

Analysis and minimization of phase noise of the digital hybrid PLL frequency synthesizer

This paper analyzes the phase noise of the digital hybrid phase locked loop (DH-PLL) frequency synthesizer that can give high speed frequency synthesis. Because noise generated by the D/A converter is added to the output phase noise, total phase noise is increased unlike in the conventional PLL. So, the aim of this paper is to minimize output phase noise for pure signal synthesis. Mathematical models of three noise sources such as input reference noise, D/A converter noise due to the quantization error and VCO noise are derived and analysed to get the minimum phase noise. Phase noise analysis of the DH-PLL is studied by the closed loop bandwidth and frequency synthesis division ratio (N). From the analysis and simulation results, we can deduce that the DH-PLL system has optimum performance for phase noise and switching speed. Schematic simulation results by the practical devices are verified to be consistent with the analysis results.