Input Queues Research Articles

Efficient Multicast Support in High-Speed Packet Switches

The tremendous growth of the Internet coupled with newly emerging applications has created a vital need for multicast traffic support by backbone routers and ATM switches. Considerable research work has been done on Input Queued (IQ) switches to handle multicast traffic flows. Unfortunately, all previously proposed solutions were of no practical value because they either lack performance or were simply too complex to implement. Internally Buffered Crossbar (IBC) switches, where a limited small amount of memory is added in each crosspoint of the crossbar fabric, on the other hand, have been considered as a robust alternative to buffer-less crossbar switches to improve the switching performance. However, very little has been done on multicasting in IBC switches. In this paper, we fill this gap and study the multicasting problem in IBC switches. In particular, we propose a novel IBC based multicast architecture along with a simple scheduling scheme named Multicast cross-point Round Robin (MXRR). Our scheme was shown to handle multicast traffic more efficiently and far better than all previous schemes for both the multicast FIFO architecture as well as the multicast k FIFO queues architecture. Yet, MXRR is both practical and achieves high performance.

Multiple-Input-Buffer and Shared-Buffer Architectures for Optical Packet- and Burst-Switching Networks

We present an architecture for implementing optical buffers, based on the feed-forward-buffer concept, that can truly emulate input queuing and accommodate asynchronous packet and burst operation. The architecture uses wavelength converters and fixed-length delay lines that are combined to form either a multiple-input buffer or a shared buffer. Both architectures are modular, allowing the expansion of the buffer at a cost that grows logarithmically with the buffer depth, where the cost is measured in terms of the number of switching elements, and wavelength converters are employed. The architectural design also provides a tradeoff between the number of wavelength converters and their tunability. The buffer architectures proposed are complemented with scheduling algorithms that can guarantee lossless communication and are evaluated using physical-layer simulations to obtain their performance in terms of bit-error rate and achievable buffer size.

Captured-frame matching schemes for scalable input-queued packet switches

Single-stage input-queued (IQ) switches are attractive for implementation of high performance routers because they require no speedup in the used memory. It has been shown that IQ switches can provide 100% throughput under admissible traffic when using maximum-weight matching schemes or iterative maximal-weight matching schemes with a speedup of two or more. These different approaches require either high computation complexity or high memory costs that can make them infeasible. Therefore, there is a need for low-complexity and fast matching schemes that provide high throughput under several admissible traffic patterns, including those with nonuniform distributions, without recurring to speedup nor multiple iterations. In this paper, we introduce the concept of captured frame and apply it to matching schemes. As a result, we propose two weightless matching schemes, one based on round-robin selection, called uFORM, and the other based on random selection, called uFPIM. We analyze the throughput improvement achieved by uFPIM, and show that these matching schemes provide high throughput under a variety of admissible traffic patterns, including those with nonuniform distributions, when using a single iteration and no speedup. Furthermore, we study the scalability of the captured-frame concept in matching schemes for memory-space-memory multiple-stage Clos-network switches, and show the achieved high switching performance and low implementation complexity.

An Efficient Packet Scheduling Algorithm With Deadline Guarantees for Input-Queued Switches

Input-queued (IQ) switches overcome the scalability problem suffered by output-queued switches. In order to provide differential quality of services (QoS), we need to efficiently schedule a set of incoming packets so that every packet can be transferred to its destined output port before its deadline. If no such a schedule exists, we wish to find one that allows a maximum number of packets to meet their deadlines. Recently, this problem has been proved to be NP-complete if three or more distinct deadlines (classes) are present in the set. In this paper, we propose a novel algorithm named Flow-based Iterative Packet Scheduling (FIPS) for this scheduling problem. A key component in FIPS is a non-trivial algorithm that solves the problem for the case where two classes are present in the packet set. By repeatedly applying the algorithm for two classes, we solve the general case of an arbitrary number of classes more efficiently. Applying FIPS to a frame-based model effectively achieves differential QoS provision in IQ switches. Using simulations, we have compared FIPS performance with five well-known existing heuristic algorithms including Earliest-Deadline-First (EDF), Minimum-Laxity-First (MLF) and their variants. The simulation results demonstrate that our new algorithm solves the deadline guaranteed packet scheduling problem with a much higher success rate and a much lower packet drop ratio than all other algorithms.

Exploring Load Balancing of a Parallel Switch with Input Queues

Parallel switch is an emerging switch technology by which we can build a high capacity switching system (such as a terabit or higher switch) from many small switch fabrics. This paper refers to the parallel switch with input queues as the Buffered Parallel Switch (BPS) and address the open issue of load-balancing for switch fabrics working parallelly and independently. Two classes of definition which depict the load balancing in different ways are proposed. Then conditions for BPS load balancing are analyzed and a family of distributed scheduling algorithms is presented. At last, a simple and efficient scheduling algorithm which can satisfy both classes of definition in a BPS without speedup is developed. Simulation results show the validity and performance of the load-balancing algorithm. Practical implementation of the distributed scheduling algorithms is also discussed.

A novel multicast mechanism for optical local area networks

In this paper, we propose a simple and efficient multicast scheduling algorithm, the Lookback Queue Access (LBQA) protocol for the employment in an asynchronous WDM optical star network. Network nodes use ALOHA based random access schemes to send their reservation packets over a common packet reservation control channel. A central traffic scheduler is allocated to coordinate message transmissions. The central scheduler carries out the LBQA scheme in real time in two phases. The first phase is to search (through input queues) for a candidate multicast message that can be sent, without partition, to all of its intended recipients. If phase 1 fails, the second phase is then activated to efficiently partition a multicast message into multiple transmissions. Performance results conducted via simulations have revealed that networks employing such a scheduling mechanism can exhibit superior network throughput levels and delay performances. To obtain sustainable high performances, we further propose an interconnected dual-star structure employed with the enhanced scheduling mechanism, the DS_LBQA algorithm. By using a simple heuristic approach, the DS_LBQA scheme is able to successfully exploit the inter data channels and properly utilize the wavelength reuse property of the intra data channels. Performance results have demonstrated the merits of deploying the DS_LBQA multicast algorithm in such a dual-star structure.

Measurement of Processing and Queuing Delays Introduced by an Open-Source Router in a Single-Hop Network

Measurement of the main contributions to the single-hop delay introduced by an open-source router is dealt with. A new method is proposed, which is capable of distinguishing the time interval during which a generic packet stays in either input or output queue (queuing delay) of the router under analysis and the time interval characterizing the effective routing process (processing delay) the packet undergoes. Thanks to proper measurement probes, i.e., kernel-layer functions, the method makes the occurring time of events of interest available at the application layer, thus giving the possibility of separately evaluating the aforementioned delays and, ultimately, pursuing a deeper insight of the considered router. After brief remarks concerning various delays a packet experiences when passing through a generic router, the measurement principle underlying the method is presented in detail. Particular emphasis is put on its capability of locally monitoring the transit of each packet from the input to the output port of an open-source router along with main features and implementation issues of the proposed measurement probes. Results obtained in many experiments carried out on a suitable test bed in different operating conditions are then given in order to highlight the method's reliability and effectiveness.

Maximizing throughput in multi-queue switches

We study a basic problem in Multi-Queue switches. A switch connectsm input ports to a single output port. Each input port is equipped with an incoming FIFO queue with bounded capacityB. A switch serves its input queues by transmitting packets arriving at these queues, one packet per time unit. Since the arrival rate can be higher than the transmission rate and each queue has limited capacity, packet loss may occur as a result of insufficient queue space. The goal is to maximize the number of transmitted packets. This general scenario models most current networks (e.g. IP networks) which only support a “best effort” service in which all packet streams are treated equally. A 2-competitive algorithm for this problem was designed in [5] for arbitraryB. Recently, a (17/9 ≈ 1.89)-competitive algorithm was presented forB>1 in [3]. Our main result in this paper shows that forB which is not too small our algorithm can do better than 1.89, and approach a competitive ratio ofe/(e − 1) ≈ 1.58.

Providing latency guarantees for the bursty traffic in multiple queues by fast switching method with bandwidth non-dividing

The Internet Engineering Task Force (IETF) has proposed a Guaranteed Service (GS) for integrated services with delay and bandwidth guarantees. This paper develops a virtual model which satisfies the performance requirements for both bandwidth reducing and delay guarantees for bursty traffic in multiple input queues. The present study reveals that the delay can be controlled by choosing appropriate values of the selection probability. Selection probability is defined as the probability of the first packet in a particular queue being selected successfully for transmissions. Using this approach, the delay can be controlled such that it falls within a tolerable range without the need for bandwidth division. The present study focuses both on the delay guarantee and less bandwidth exhausting. It is found that there is excellent agreement between the numerical simulation results and the mathematical analysis. The approach developed in this paper can be applied to any high- speed network as a means of obtaining performance improvements.

Throughput analysis of a buffered crossbar switch with multiple input queues under burst traffic

This letter derives the saturated throughput for a buffered crossbar switch with multiple queues at each input port under uniform burst traffic. The accuracy of the theoretic analysis is also investigated by extensive simulation.

Analysis of Distributed DDQ for QoS Router

In a packet switching network, congestion is unavoidable and affects the quality of real-time traffic with such problems as delay and packet loss. Packet fair queuing (PFQ) algorithms are well-known solutions for quality-of-service (QoS) guarantee by packet scheduling. Our approach is different from previous algorithms in that it uses hardware time achieved by sampling a counter triggered by a periodic clock signal. This clock signal can be provided to all the modules of a routing system to get synchronization. In this architecture, a variant of the PFQ algorithm, called digitized delay queuing (DDQ), can be distributed on many line interface modules. We derive the delay bounds in a single processor system and in a distributed architecture. The definition of traffic contribution improves the simplicity of the mathematical models. The effect of different time between modules in a distributed architecture is the key idea for understanding the delay behavior of a routing system. The number of bins required for the DDQ algorithm is also derived to make the system configuration clear. The analytical models developed in this paper form the basis of improvement and application to a combined input and output queuing (CIOQ) router architecture for a higher speed QoS network.

A fractal Poisson process and its input queue

An interrupted Poisson process has two states, on-state and off-state. In the onstate, Poisson arrivals occur, and on the other hand, there are no arrivals in the off-state. As the variation becomes larger, the arrival process is changed to a more complex interrupted Poisson process generated by embedding new off-states in each on-state. In such a way, recursively embedding offstates in on-states and taking a limit, a fractal structure can be found in the on-off structure. We name the arrival process fractal Poisson process and study it. The interarrival time density has a heavy tail. In addition, we study queueing models with the fractal Poisson arrivals. Even if the utilization is very low, the waiting time is very long.

Multicast Scheduling in Buffered Crossbar Switches with Multiple Input Queues

Multicast Scheduling in Buffered Crossbar Switches with Multiple Input Queues

High-performance switching based on buffered crossbar fabrics

As buffer-less crossbar scheduling algorithms reach their practical limitations due to higher port numbers and data rates, internally buffered crossbar (IBC) switches have gained a lot of interest recently due to their great potential in solving the complexity and scalability issues faced by their buffer-less predecessors. The IBC switching architecture combined with the virtual output queueing (VOQ) architecture was shown, through distributed scheduling algorithms, to be able to sustain the current and expected increases in Internet throughput rates. Due to the architectural similarity between the input queued (IQ) and IBC switches, all the algorithms proposed for the latter were just a simple mapping of earlier algorithms proposed for the former. In this paper, we propose a set of scheduling schemes that are purely advocated for the VOQ/IBC switch architecture. We first address the issue of the internal buffers importance in the arbitration process. We propose a weighted scheduling algorithm, named Critical internal Buffer First (CBF), which takes full advantage of the internal buffer elements and makes its decision exclusively on the internal buffer information. Second, in order to simplify the scheduling scheme and make it practical, we propose a class of scheduling algorithms, named Current Arrival First–Priority Removal (CAF–PRMV) that use priority levels instead of weights. We argue that the interaction, through the internal buffer element, between the input and output schedulers is very important in designing such practical and highly scalable schemes for the IBC switching architecture. Our hardware implementation, in reconfigurable logic, shows that our CAF–PRMV class of algorithms can sustain a 10 Gbps line speed for a 32 × 32 VOQ/IBC switch.

Queueing network models of credit-based flow control

Credit-based flow control schemes are a commonly used means of preventing buffer overflow in high-speed networks spanning a local area. Fibre Channel, a widely-used storage area networking technology, and InfiniBand, a recently developed system area network technology, are examples of two network technologies that employ credit-based flow control. With credit-based flow control, the receiver sends credits to the sender to indicate the availability of receive buffers; the sender waits for credits before transmitting messages to the receiver. We present two models of credit-based flow control operation. In particular, we consider a fork-join queueing system with two input queues; the message population feeds one queue and the credit population the other. We consider the case of bulk message arrivals and single arrivals drawn from a finite population. Our analysis yields stationary probability distributions for message queue length and number of available credits. We provide equations for mean message queue length, mean number of credits, throughput, and mean message waiting time.

Cell switching versus packet switching in input-queued switches

Input Queued (IQ) switches have been well studied in the past two decades by researchers. The main problem concerning IQ switches is scheduling the switching fabric in order to transfer packets from input ports to output ports. Scheduling is relatively easier when all packets are of the same size. However, in practice, packets are of variable length. In the current implementation of switches, variable length packets are segmented into fixed length packets-also knowns as cells-for the purpose of scheduling. However, such cell-based switching comes with some significant disadvantages: (a) loss of bandwidth due to the existence of incomplete cells; and (b) additional overhead of segmentation of packets and re-assembly of cells. This is a strong motivation to study packet-based scheduling, i.e., scheduling the transfer of packets without segmenting them. The problem of packet scheduling was first considered by Marsan et al. They showed that under any admissible Bernoulli IID (independent and identically distributed) arrival traffic, a simple modification of the Maximum Weight Matching (MWM) algorithm achieves 100% throughput. In this paper, we first show that no work-conserving (i.e., maximal) packet-based algorithm is stable for arbitrary admissible arrival processes. Thus, the results of Marsan et al. are strongly dependent on the arrival distribution. Next, we propose a new class of waiting algorithms. We show that the waiting-MWM algorithm is stable for any admissible traffic using the fluid limit technique. We would like to note that the algorithms presented in this paper are distribution independent or universal. The algorithms and proof methods of this paper may be useful in the context of other scheduling problems.

Smooth switching problem in buffered crossbar switches

Scalability considerations drive the switch fabric design to evolve from output queueing to input queueing and further to combined input and crosspoint queueing (CICQ). However, few CICQ switches are known with guaranteed quality of service, and credit-based flow control induces a scalability bottleneck. In this paper, we propose a novel CICQ switch called the smoothed buffered crossbar or sBUX, based on a new design objective of smoothness and on a new rate-based flow control scheme called the smoothed multiplexer or sMUX. It is proved that with a buffer of just four cells at each crosspoint, sBUX can utilize 100% of the switch capacity to provide deterministic guarantees of bandwidth and fairness, delay and jitter bounds for each flow. In particular, neither credit-based flow control nor speedup is used, and arbitrary fabric-internal latency is allowed between line cards and the switch core.

Combined input and output all-optical variable buffered switch architecture for future optical routers

We present a novel optical packet switching fabric architecture incorporating both input single-stage and output multistage all-optical variable delay buffers as combined input and output queues. For a given optical buffer size (1000 B), the proposed architecture, which has combined input and output optical variable buffer queues with optimum partition, achieves packet loss rates (3.4E-5) that are three orders of magnitude lower than the case without the variable buffers and two orders of magnitude lower than the cases with input or output optical queues alone.

On the Stability of Isolated and Interconnected Input-Queueing Switches Under Multiclass Traffic

In this correspondence, we discuss the stability of scheduling algorithms for input-queueing (IQ) and combined input/output queueing (CIOQ) packet switches. First, we show that a wide class of IQ schedulers operating on multiple traffic classes can achieve 100% throughput. Then, we address the problem of the maximum throughput achievable in a network of interconnected IQ switches and CIOQ switches loaded by multiclass traffic, and we devise some simple scheduling policies that guarantee 100% throughput. Both the Lyapunov function methodology and the fluid modeling approach are used to obtain our results.

Multi-wavelength switching in IP optical nodes adopting different buffering strategies

The paper addresses the topic of long-haul optical networking for the provision of large-bandwidth IP services. A class of optical packet switching architectures is considered which adopts an arrayed wavelength grating device as packet router. The architecture performs slotted packet switching operations and fully exploits the wavelength routing capabilities by allowing multi-wavelength switching. Fiber delay lines are used to perform optical packet buffering, which accomplishes either input queueing or shared queueing. Here a thorough performance evaluation is carried out with different buffering configurations and the effect of various switch parameters on traffic performance is studied.