Input-queued ATM Switch Research Articles

The Single Bit Request Grant (SBRG) Scheduling Algorithm for Input-Queued ATM Switches

In this paper, we propose an efficient single-iteration single-bit request scheduling algorithm for input-queued ATM switches that based on a new arbitration technique called the Single Bit Request Grant (SBRG) algorithm. The operation of the SBRG depends on the concept known as “the preferred input-output pairs first”, and the arbitration requests starts from switch output ports to reduce the number of issued request signals. Compared to other single-iteration algorithms, simulation results show that the SBRG maximizes the match size and improves the switch delay/throughput performance, especially when the load increases. Also, the proposed algorithm reduces the complexity of some of the existing algorithms by decreasing the number of input-output transferred messages, and by the absence of any encoding/decoding mechanism that can be used in some existing algorithmsto reduce the size of request signals to one bit.

A Comparative Study of Single-Iteration Scheduling Algorithms for Input-Queued ATM Switches

A Comparative Study of Single-Iteration Scheduling Algorithms for Input-Queued ATM Switches

Design of pipelined routing engine for input-queued ATM switches

A highly efficient virtual output queue routing engine for an advanced input-queued ATM switch, which has a multi-gigabit serial crossbar structure, is proposed. Using a pipelined approach the proposed routing engine provides wire-speed routing with low cost and tolerates the transmission pipeline latency of request and grant data.

Learning-automata-based scheduling algorithms for input-queued ATM switches

A new algorithm for scheduling cells in input-queued ATM switches is introduced. The proposed algorithm makes use of learning automata, in order to achieve a high throughput and a low latency, even when the offered traffic is bursty.

Window-based cell scheduling algorithm for VLSI implementation of an input-queued ATM switch

A method for providing bandwidth reservations in an input-buffered self-routing crossbar switch architecture is introduced and analysed. The scheme computes a conflict-free set of flows within a cell slot and achieves a link utilisation as high as 93% for uniform random bursty traffic. Simulations of the proposed algorithm have been performed for different window sizes (W = 1, 2, 4, 8) and the cell loss probability (CLP), cell waiting time (CWT) and system throughput (ST) are estimated. The VLSI implementation of the scheme is also described.

A quantitative comparison of iterative scheduling algorithms for input-queued switches

In this paper we quantitatively evaluate three iterative algorithms for scheduling cells in a high-bandwidth input-queued ATM switch. In particular, we compare the performance of an algorithm described previously – parallel iterative matching (PIM) – with two new algorithms: iterative round-robin matching with slip ( iSLIP) and iterative least-recently used ( iLRU). We also compare each algorithm against FIFO input-queueing and perfect output-queueing. For the synthetic workloads we consider, including uniform and bursty traffic, iSLIP performs almost identically to the other algorithms. Cases for which PIM and iSLIP perform poorly are presented, indicating that care should be taken when using these algorithms. But, we show that the implementation complexity of iSLIP is an order of magnitude less than for PIM, making it feasible to implement a 32×32 switch scheduler for iSLIP on a single chip.

Provisioning QoS features for input-queued ATM switches

A new scheduling algorithm is proposed to improve on existing algorithms designed for input-queued ATM switches. By assigning a session weight according to its queue length normalised by its rate and using maximum weight matching to obtain a match, the proposed algorithm can avoid starvation of slow sessions, thus providing good delay properties as well as fair services, and at the same time reducing traffic burstiness.

Performance of an input-queued ATM switch with even/odd switching planes

A switch architecture is proposed for alleviating the HOL blocking by employing even/odd dual FIFO queues at each input and even/odd dual switching planes dedicated to each even/odd queue. Under random traffic, it gives 76.4% throughput without output expansion and 100% with output expansion r = 2, with the same amount of crosspoints as for the ordinary output expansion scheme.

Saturation throughput analysis of an input queueing ATM switch with multiclass bursty traffic

We consider an N/spl times/N non-blocking, space division ATM switch with input cell queueing. At each input, the cell arrival process comprises geometrically distributed bursts of consecutive cells for the various outputs. Motivated by the fact that some input links may be connected to metropolitan area networks, and others directly to B-ISDN terminals, we study the situation where there are two classes of inputs with different values of mean burst length. We show that when inputs contend for an output, giving priority to an input with smaller expected burst length yields a saturation throughput larger than if the reverse priority is given. Further, giving priority to less bursty traffic can give better throughput than if all the inputs were occupied by this less bursty traffic. We derive the asymptotic (as N/spl rarr//spl infin/) saturation throughputs for each priority class. >

Optimum architecture for input queuing ATM switches

An input queueing ATM switch architecture employing the contention resolution called ‘scheduling algorithm’ is described. A high efficiency of over 90% can be achieved without any considerable increase in the amount of hardware or contention control speed.