Input Protection Circuit Research Articles

The Development of an Input Protective Circuit of the Radio Frequency (RF) Path of the High Frequency (HF) Band Receiver

The article presents the results of the input protection circuitdevelopment, the main purpose of which is to limit the signals of high-power entering the HF receiverRF path on the antenna input. The input protection circuit protects the sensitive components and elements of the receiver from overload and failure.The need to ensure the reliability and safety of complex communication systems and complexes is only increasing every year.The relevance of input circuitprotection may occur at small separation of the receiver and the source of interference, under the conditions of electronic warfare. The principle of the developed circuit is based on the relay switchcontrol.The method for selecting the parameters of circuitcomponents is described.The practicalprototype tests of the input protection circuit were carried out, being installed at the input of the manufactured HF band receiver. During the practical experiment, shortcomings were identified that were not revealed in the simulation model built in the NI Multisim environment.In particular, it is a local heating of the two components on the printed circuit board, caused primarily by capacitive resistance and weak filter attenuation introduced within the range of 23…30 MHz. Theways to improve the existing protection circuit are noted. An important feature of the circuit is that after minor modification of the input detector contour, the developed circuit can be used at VHF frequencies, up to 520 MHz.The advantages of the scheme should also include a short response time - 1.27 ms, insertion attenuation - less than 0.01 dBm. The product remains operational after applying a sinusoidal RF signal on the antenna input for 15 minutes with an EMF of 100V in the operating frequency range.

Идентификация элементов измерительной части цифровой релейной защиты по времени ее срабатывания

The purpose of the study is to develop an identification method of a specific implementation of the elements of the measuring part (intermediate converters, analog filters) and partially computational-logical part (digital filters) of a microprocessor relay protection by the signal actuation time, which, unlike the existing approaches allows to identify and exclude the delays introduced by the executive protection elements. The method of directed graphs is used to form a mathematical model of the measuring part of the microprocessor relay protection. The solution formed as a result of differential equations is implemented using the method of analog implicit continuous integration. The time delays introduced by the input protection circuits are determined as follows: identical signals are fed to the terminal and the mathematical model of protection; signal actuation time is recorded, where the time starting point is the moment the input signal reaches the setpoint and the end point is the moment of the actuation signal occurrence. Having studied 144 different combinations of measuring part elements (intermediate converters, analog filters) and digital filters with a finite impulse response of microprocessor relay protection, the most “optimal” combination has been chosen, which features the least deviation from the response time of a real device in all studied modes as compared with other combinations. The proposed identification method of input circuit elements of microprocessor (numerical) protection is the main way to bring the model closer to a real device. It also enables to receive a table of “typical” response times of protections with the different structure of the measuring part and depending on the specific type of protection terminal choose in practice a predetermined “optimal” internal composition of protection used when setting up protection using their mathematical models.

A Fully Integrated 16-Channel Closed-Loop Neural-Prosthetic CMOS SoC With Wireless Power and Bidirectional Data Telemetry for Real-Time Efficient Human Epileptic Seizure Control

A 16-channel closed-loop neuromodulation system-on-chip (SoC) for human epileptic seizure control is proposed and designed. In the proposed SoC, a 16-channel neural-signal acquisition unit (NSAU), a biosignal processor (BSP), a 16-channel high-voltage-tolerant stimulator (HVTS), and wireless power and bidirectional data telemetry are designed. In the NSAU, the input protection circuit is used to prevent MOSFET from overstressing by the high-voltage stimulations. Hence, NSAUs can share electrodes with stimulators. The auto-reset chopper-stabilized capacitive-coupled instrumentation amplifiers (AR-CSCCIAs) are designed with the chopper-stabilized technique with a new offset reduction loop. The measured input-referred noise is 2.09 $\mu \textrm {V}_{\mathrm {rms}}$ and the noise-efficiency factor (NEF) is 3.78. The entropy-and-spectrum seizure detection algorithm is implemented in the BSP with 0.76-s seizure detection latency and 97.8% detection accuracy. When the seizure onset is detected by the BSP, the HVTS with adaptive supply control delivers 0.5–3-mA biphasic current stimulation to suppress the seizure onset. The proposed SoC is powered wirelessly, and the bidirectional data telemetry is realized through the same pair of coils in 13.56 MHz. The downlink data rate is 211 Kb/s with the binary phase-shift keying (BPSK) modulation and a new BPSK demodulator. The uplink data rate is 106 Kb/s with the load-shift keying (LSK) modulation. The proposed SoC is fabricated in a 0.18- $\mu \text{m}$ CMOS technology and occupies 25 mm2. Electrical tests have been performed to characterize the SoC performance. In vivo animal experiments using mini-pigs have been performed to successfully verify the closed-loop neuromodulation functions on epileptic seizure suppression.

A 16-Channel CMOS Chopper-Stabilized Analog Front-End ECoG Acquisition Circuit for a Closed-Loop Epileptic Seizure Control System.

In this paper, a 16-channel analog front-end (AFE) electrocorticography signal acquisition circuit for a closed-loop seizure control system is presented. It is composed of 16 input protection circuits, 16 auto-reset chopper-stabilized capacitive-coupled instrumentation amplifiers (AR-CSCCIA) with bandpass filters, 16 programmable transconductance gain amplifiers, a multiplexer, a transimpedance amplifier, and a 128-kS/s 10-bit delta-modulated successive-approximation-register analog-to-digital converter (SAR ADC). In closed-loop seizure control system applications, the stimulator shares the same electrode with the AFE amplifier for effective suppression of epileptic seizures. To prevent from overstress in MOS devices caused by high stimulation voltage, an input protection circuit with a high-voltage-tolerant switch is proposed for the AFE amplifier. Moreover, low input-referred noise is achieved by using the chopper modulation technique in the AR-CSCCIA. To reduce the undesired effects of chopper modulation, an improved offset reduction loop is proposed to reduce the output offset generated by input chopper mismatches. The digital ripple reduction loop is also used to reduce the chopper ripple. The fabricated AFE amplifier has 49.1-/59.4-/67.9-dB programmable gain and 2.02-μVrms input referred noise in a bandwidth of 0.59-117 Hz. The measured power consumption of the AFE amplifier is 3.26 μW per channel, and the noise efficiency factor is 3.36. The in vivo animal test has been successfully performed to verify the functions. It is shown that the proposed AFE acquisition circuit is suitable for implantable closed-loop seizure control systems.

Leakage current-induced effects in the silicon microstrip and gas electron multiplier readout chain and their compensation method

Leakage current flowing into the charge sensitive amplifier (CSA) is a common issue in many radiation detection systems as it can increase overall system noise, shift a DC baseline or even lead a recording channel to instability. The commonly known leakage current contributor is a detector, however other system components like wires or an input protection circuit may become a serious problem. Compensation of the leakage current resulting from the electrostatic discharge (ESD) protection circuit by properly sizing its components is possible only for a narrow temperature range. Moreover, the leakage current from external sources can be significantly larger. Many applications, especially High Energy Physics (HEP) experiments, require a fast baseline restoration for high input hit rates by applying either a low-value feedback resistor or a high feedback resistance combined with a pulsed reset circuit. Leakage current flowing in the feedback in conjunction with a large feedback resistance supplied with a pulsed reset results in a significant voltage offset between the CSA input and output which can cause problems (e.g. fake hits or instability). This paper shows an issue referred to the leakage current of the ESD protection circuit flowing into the input amplifier. The following analysis and proposed solution is a result of the time and energy readout ASIC project realization for the Compressed Baryonic Matter (CBM) experiment at FAIR (Facility for Antiproton and Ion Research) in Darmstadt, Germany. This chip is purposed to work with microstrip and gaseous detectors, with high average input pulses frequencies (250 kHit/s per channel) and the possibility to process input charge of both polarities. We present measurements of the test structure fabricated in UMC 180 nm technology and propose a solution addressing leakage current related issues. This work combines the leakage current compensation capabilities at the CSA level with high, controllable value of the amplifier feedback resistor independent of the leakage current level and polarity. The simulation results of the double, switchable, Krummenacher circuit-based feedback application in the CSA with a pulsed reset functionality are presented.

ARTROC—a readout ASIC for GEM-based full-field XRF imaging system

In the paper we report on development of an Application Specific Integrated Circuit (ASIC), called ARTROC, being part of a full-field X-ray fluorescence spectroscopy (XRF) imaging system equipped with a standard three stage Gas Electron Multiplier (GEM) detector of 10×10 cm2 area. The ARTROC consists of 64 independent channels, allowing for simultaneous recording of the amplitudes (energy sub-channel) and time stamps (timing sub-channel) of incoming signals. Thanks to the implemented token-based read out of derandomizing buffers, the ASIC also provides data sparsification and full zero suppression. Reconstruction of the hit positions is performed in an external data acquisition system by matching the time stamps of signals recorded in X- and Y-strips. The amplitude information is used for centre of gravity finding in clusters of signals on neighbouring strips belonging to the same detection events. The ASIC could work in one of six gain modes and one of two speed modes. In a slower mode the maximum count rate per channel is 105/s while in a faster mode it is three times higher. The ARTROC comprises also input protection circuits against possible random discharges inside active detector volume, so it can be used without any additional input components. The ASIC has been designed in 350 nm CMOS process. The basic functionality and parameters have been evaluated using the testability functions implemented in the ASIC design. The ASIC has been also tested in a fully equipped GEM detector set-up with X-rays source.

Protection circuits for ultrasound applications

A simple input protection circuit for ultrasound pulse-echo applications is described. Its performance is analyzed with regard to other widely used arrangements. Besides the primary function of showing high impedance during the transducer excitation time and a low impedance path to the amplifier in reception, issues of harmonic distortion, insertion losses, bandwidth, power dissipation, transient response, and noise are addressed. It is shown that the proposed circuit has many advantages, operating without any control signals or bias voltages. It is small and can be considered a good general-purpose protection circuit alternative.

Native-NMOS-Triggered SCR With Faster Turn-On Speed for Effective ESD Protection in a 0.13-$rm murm m$CMOS Process

In order to quickly discharge the electrostatic discharge (ESD) energy and to efficiently protect the ultrathin gate oxide, a novel native-negative-channel metal oxide semiconductor (NMOS)-triggered silicon-controlled rectifier (NANSCR) is proposed for on-chip ESD protection in a 0.13- $ mu m$ complementary metal oxide semiconductor (CMOS) process with a voltage supply of 1.2 V. The proposed NANSCR can be designed for the input, output, and power-rail ESD protection circuits without latchup danger. A new whole-chip ESD protection scheme realized with the proposed NANSCR devices is also demonstrated with the consideration of pin-to-pin ESD stress. From the experimental results, the trigger voltage, holding voltage, turn-on resistance, turn-on speed, and charged-device-model (CDM) ESD level of NANSCR can be greatly improved, as compared with the traditional low-voltage-triggering SCR (LVTSCR). Under transmission line pulsing (TLP) stress, the gate leakage current of the gate monitor device protected by the proposed NANSCR is monitored after each TLP pulse, whereas the gate leakage current is not obviously increased. Therefore, the ultrathin gate oxide of the input stage can be safely protected by the new proposed NANSCR against ESD stress in the nanoscale CMOS technology.

1.5 V high-speed electrostatic dischargefree BiCMOS digital circuit

A novel circuit design that effectively eliminates the need for input protection circuits is described. Besides having an excellent electrostatic discharge (ESD) robustness, the simulation results have shown that this design outperforms current BiCMOS circuits in terms of speed, power, crossover capacitance, and chip area for a wide range of load capacitances, power supply voltages and technologies. The proposed circuit remains functional after an ESD test.

Improving the ESD performance of input protection circuits in retrograde well and STI structures

We investigate the current transport characteristics of input protection devices using LOCOS and STI structures in the retrograde well. We show that the carriers flow through the concave well doping region between the field and well doping areas in the retrograde well. In the STI structure, the current path in the substrate is restricted to the region adjacent to the STI boundary.

An investigation of BiCMOS ESD protection circuit elements and applications in submicron technologies

The characteristics of individual protection circuit elements, the npn and the NMOS transistors, in a 0.8 μm BiCMOS technology have been evaluated, and their use in ESD protection circuits have been discussed in some detail. Both the output and input protection circuits have been developed using npn transistors as the primary protection elements. The design requirements and limitations of these circuits are analyzed. ESD thresholds of > 4kV have been obtained for both input and output buffers in this technology.

A high rate preamplifier for use with a gas proportional counter

In the development of detectors for use with synchrotron radiation, a serious limit to the maximum counting rate is frequently determined by the signal processing speed of the general purpose commercial electronic units that are often used. Therefore, in developing a high speed gas proportional counter for soft x-ray spectroscopy measurements, a major requirement has been for a high rate, low noise preamplifier. A crucial factor in meeting the required processing speed is the ability to separate out the fast electron pulse from the much slower, induced ion afterpulse and to reject the latter. In addition, all gas proportional counters suffer from occasional high voltage breakdown and so the circuit design must provide the sensitive front end of the preamplifier with sufficient transient protection. We present a design for a preamplifier circuit which offers a 30 MHz bandwidth and better than 2500 electrons rms noise. It features pulse shaping which permits the complete rejection of the ion afterpulse and an input protection circuit which has enabled the preamplifier to survive detector breakdown. The preamplifier has a measured gain of 0.6 μV per electron. The fast rise time of the preamplifier has allowed us to investigate the speed of the detector, a primary limitation of which is due to the electron diffusion rate within the counter. We describe an experiment conducted using this preamplifier to reduce the electron drift speed to <100 ns.

Variable bit organization as a new test function for standard memories

A variable bit-organization function that enables the RAM to be used in plural bit organizations is proposed. This function reduces the test time for many kinds of test patterns and data patterns. Consequently, a short-time, accurate, and severe test is realized. This test-time reduction function is important in a high-speed memory such as SRAM because it preserves the same access time for the different organizations. Using the output driver transistor as the input protection circuit, a low and uniform input/output pin capacitance of 3.5 pF and a high electrostatic discharge (ESD) immunity have also been realized. This function has been successfully implemented in a 1-Mb SRAM configurable for both 1-M-word*1-b and 256K-word*4-b organizations without any practical drawbacks. >

Low-noise wide-band amplification system for acquiring prebreakdown current pulses in liquid dielectrics

A low-noise wideband amplification system consisting of a preamplifier with input protection circuit and an amplifier were developed for measuring the prebreakdown currents in liquid dielectrics. The system design considerations and experimental results are presented. The preamplifier was voltage-sensitive with a voltage gain of 154 V/V, and had a bandwidth of 56 MHz and an equivalent noise voltage spectral density of 0.93 nV/Hz/sup 1/2/. The amplifier had a voltage gain of about 12 and a bandwidth of 58 MHz and was capable of driving mod 2 mod V across two paralleled 50 Omega loads. The overall system had a gain of 92400 V/A when loaded with 50 Omega , and it had a minimum detectable current of 1.9 mu A for an overall bandwidth of about 29 MHz. >

Bonding wire discharges in integrated circuit packages

Abstract Electrostatic discharge damage to semiconductor devices may occur as a result unwanted charge entering the input circuity. Various input protection circuits offer some degree of protection from such occurences. Another source of discharge damage, which has not been widely reported, is that from breakdown of corona discharging between the bonding wires and earthed track which surrounds the edge of the circuit wafer. Such discharges have been experimentally recorded, and using Townsend sparking criteria, analysis of results shows that such breakdown discharges are possible within the confines of the integrated circuit system.

Stability analysis ofRC oscillator using CMOS transistors

The influence of a resistorRs, which is added in series with the input protection circuit of a CMOS inverter, and the input parasitic capacitanceCs of that inverter on the oscillation-period stability is analysed in this paper. It is shown that the optimum value of the resistanceRs depends on the oscillation frequency and the timing elementsR andC.