Input-output Block Research Articles

Low Area and Power-Efficient FPGA Implementation of Improved AM-CSA-IIR Filter Design for the DSP Application

Digital Signal Processing (DSP) grew enormously in the past few decades and it was extensively practiced for numerous engineering applications like biomedical signal processing, radar signal processing, adaptive antenna design, intelligent control, etc. In DSP, the Finite Impulse Response (FIR) filter and Infinite Impulse Response (IIR) filter plays a vital role in the design of a complex signal processing system. Generally, The FIR filters are stable, linear in phase, with fewer finite-precision errors and easy to implement. However, most of the IIR filters are used in signal processing applications due to the less computational complexity which is compared to the FIR filters. Moreover, the IIR filter requires only fewer filter coefficients and requires only less amount storage registers. In this research, an IIR filter is implemented with Array multiplier and Carry Skip Adder (CSA) to improve hardware utilization. The IIR filter input is generated randomly which is stored in Random Access Memory (RAM). Similarly, the coefficient is generated by utilizing the Parks-McClellan algorithm where the generated value is stored in Read Only Memory (ROM). The proposed AM-CSA IIR (Array Multiplier-Carry Skip Adder Infinite Impulse Response) filter performances are evaluated in terms of filter output, Input Output Block (IOB), Look Up Table (LUT), Flip Flops (FF), slices, delay, and fractional delay. Overall the proposed design attained LUT= 115 (0.0564%), FF=40 (0.01%) and IOB= 22 (3.77%) and reduced fractional delay of about 0.0057ns.

Performance Analysis of AODV Routing for Wireless Sensor Network in FPGA Hardware

Wireless sensor network (WSN) is a group of interconnected sensor nodes that work wirelessly to capture the information of surroundings. The routing of the network is a challenging task. The routing of WSN is classified as proactive, reactive, and hybrid. Adhoc on-demand distance vector (AODV) routing is an example of reactive routing based on the demand route formations among different nodes in the network. The research article emphasizes the design and simulation of the AODV routing hardware chip using very-high-speed integrated circuit hardware description language (VHDL) programming in Xilinx integrated synthesis environment (ISE) 14.7 software. The performance of the chip is studied based on the field-programmable gate array (FPGA) hardware parameters such as slices, lookup table (LUTs), input/output block (IOB), flip-flops, and memory for the different configurations of the network (N = 10, 20 ….100). The delay and frequency are also estimated on the Virtex-5 FPGA. The performance of the WSN with AODV routing is also analyzed based on the packet delivery ratio, throughput, delay, and control overhead. The simulation test cases verified the 8-bit, 64-bit, and 128-bit data communication within the nodes.

A 17.5-fJ/bit Energy-Efficient Analog SRAM for Mixed-Signal Processing

An energy-efficient analog SRAM (A-SRAM) is proposed to eliminate redundant analog-to-digital (A/D) and digital-to-analog (D/A) conversion in mixed-signal systems, such as neuromorphic chips and neural networks. D/A conversion is integrated into the SRAM readout by charge sharing of the proposed split bitline (BL). Also, A/D conversion is integrated into the SRAM write operation with the successive approximation method in the proposed input–output block. Also, a configurable SRAM bitcell array is proposed to allocate the converted digital data without unfilled bitcells. The multirow access decoder selects multiple bitcells in a single column and configures the bitcell array by controlling the BL switches to split BLs. The proposed A-SRAM is implemented using the 65-nm CMOS technology. It achieves 17.5-fJ/bit energy-efficiency and 21-Gbit/s throughput for the analog readout, which are 64% and 1.3 times better than those of the conventional SRAM followed by a digital-to-analog converter (DAC). Also, the area is reduced by 91% compared with the conventional SRAM with analog-to-digital converter (ADC) and DAC.

An IO block array in a radiation-hardened SOI SRAM-based FPGA

We present an input/output block (IOB) array used in the radiation-hardened SRAM-based field-programmable gate array (FPGA) VS1000, which is designed and fabricated with a 0.5 μm partially depleted silicon-on-insulator (SOI) logic process at the CETC 58th Institute. Corresponding with the characteristics of the FPGA, each IOB includes a local routing pool and two IO cells composed of a signal path circuit, configurable input/output buffers and an ESD protection network. A boundary-scan path circuit can be used between the programmable buffers and the input/output circuit or as a transparent circuit when the IOB is applied in different modes. Programmable IO buffers can be used at TTL/CMOS standard levels. The local routing pool enhances the flexibility and routability of the connection between the IOB array and the core logic. Radiation-hardened designs, including A-type and H-type body-tied transistors and special D-type registers, improve the anti-radiation performance. The ESD protection network, which provides a high-impulse discharge path on a pad, prevents the breakdown of the core logic caused by the immense current. These design strategies facilitate the design of FPGAs with different capacities or architectures to form a series of FPGAs. The functionality and performance of the IOB array is proved after a functional test. The radiation test indicates that the proposed VS1000 chip with an IOB array has a total dose tolerance of 100 krad(Si), a dose survivability rate of 1.5 × 1011 rad(Si)/s, and a neutron fluence immunity of 1 × 1014 n/cm2.

Integration of Macroeconomic Behavioural Relationships and the Input-Output Block (Romanian Modelling Experience)

The last version of the Romanian macromodel (Dobrescu 2005b) incorporates the experience accumulated through the utilisation of its previous forms - either experimental (Dobrescu 1991-1994) or operational (Dobrescu 1996-2005a). At the same time, it introduces some methodological and informational improvements. The most significant of them is the structural decomposition of economy, according to the input-output techniques. Output and absorption are divided into: a) agriculture, sylviculture, forestry, hunting, and fishing; b) mining and energy; c) manufacturing industry; d) construction; e) transport, post and communications; f) trade and services. These categories can be easily translated into the classical three-sectors classification: primary (a+b), secondary (c+d), and tertiary (e+f). Due to the relatively advanced stage of the transitional processes in Romania, the behavioural functions were modelled - as much as possible - by the standard relationships. Besides, unlike the previous versions (that used statistical series beginning with 1980) the present one is based exclusively on information regarding the period 1989-2004. Since the input-output tables are defined yearly, the model contains only annual indicators. They are expressed in denominated local currency (RON). The export, import, and exchange rate series were transformed in Euro. When there were several informational sources for the same indicator, the data extracted or derived from national accounts have been adopted. The statistical series are relatively short and often fractured (because of the transforming processes of transition). Although, it is known that ADF test of stationarity does not offer reliable results in the case of limited number of observations, generally the series satisfying it were used. The simplest regression methods were also preferred. The structural breaks in evolution of some series have been dealt by the inclusion of dummies. Obviously, all these circumstances weaken the stability of econometric coefficients that must be continuously updated. The first two chapters of the paper characterise the main macroeconomic behavioural relationships and input-output coefficients. The third one discusses a possible scenario for the Romanian economy during 2005-2010. A set of simulations is presented in the final part of the paper; these reveal some operational features of the macromodel.

Dynamic testing of Xilinx Virtex-II field programmable gate array (FPGA) input/output blocks (IOBs)

Heavy-ion irradiation and fault injection experiments were conducted to evaluate the upset sensitivity of the Xilinx Virtex-II field programmable gate arrays (FPGAs) input/output block (IOB). Full triple module redundancy (TMR) of the IOBs, in combination with regular configuration scrubbing, proved to be a quite effective upset mitigation method.

Input-output block decoupling of linear time-varying singular systems

The input-output block decoupling problem by state feedback is studied for linear time-varying singular systems. First, an algorithm, the regularization algorithm, is developed such that the system can be made by state feedback to have a unique impulse-free solution. Second, another algorithm, the block decoupling algorithm, is proposed, which provides sufficient conditions for the solvability of the input-output block decoupling problem. Then, a decoupling feedback law is constructed such that the corresponding closed-loop system is regular, impulse-free, and noninteractive. Finally, an example is given to illustrate the applicability of the algorithms.

Block Decoupling of Generalized State Space Systems

The problem of input-output block decoupling of generalized state space systems, via a regular static state feedback law, is studied for the first time. The necessary and sufficient conditions for the problem to have a solution are established. The necessary and sufficient conditions for block decoupling with simultaneous stabilizability, and the necessary and sufficient conditions for block decoupling with simultaneous arbitrary assignment of the system poles are established. © 1997 Elsevier Science Ltd.

Impacts of regional transportation improvements on urban development in Japan

Urban agglomerations in Tokyo and Osaka in post-war period are largely attributable to the policies underlying the four National Development Plans implemented in that period. These policies, which were originally intended to achieve an effect on the opposite of agglomeration, relate primarily to the high-speed transit network known as the Tokaido shinkasen and the expressway segments linking the Kanto and Kansai regions. For the purpose of capturing the historical scenario of regional agglomeration, we have formulated a long-term macro-econometric model from 1950–85, with 5-year simulation cycles. This constitutes an employment distribution block, an input-output block, and an inter-prefectural activities block, incorporating all major macro-variables. In an earlier stage of this research the model was calibrated and the total tests upon all formulations were completed. Ascertaining that the accuracy of the model is well within permissible limits, an evaluation of policy scenarios due to the delay in the introduction of the shinkansen on the Tokaido line, has been conducted. Results indicate that Tokyo grows much less rapidly than in reality, Osaka maintains the same rate of growth, and the other areas show a substantial growth by 1985. In the present version, we improve on the model with respect to its qualitative performance by relaxing the exogeneity of national employment and GNP to allow for the evaluation of these policy variables. In completing these final tests on the model, we are able to confirm the validity of the model by demonstrating its accuracy to be in a satisfactory range. In a case study, the policy areas that have contributed to the present distribution of development have been explored in detail. Comparative policy transformations, necessary to achieve the opposite effects to agglomeration, are discussed.