Parallel Input Data Research Articles

Detection of The Lower Limb Asymmetries and Discomfort Considering Foot Pressure as an Attribute

A greater number of diseases and chronic conditions are making their presence since more than a decade. It has really taken its toll during the COVID-19 period. Our concern is totally the lower part of our body which includes the hip portion along with upper thigh, knees, lower limbs and ankles. Some diseases which we have surveyed has been taking place as such are Achilles’s tendonitis, arthritis in the ankle or ankles, bunions, hammertoes, plantar pressure diseases, et cetera. There are also a lot of conditions associated with lower limb muscles such as irregular muscle toning, muscle stressing, fatigue, et cetera which takes place in individuals of almost all kinds of ages. In order to nullify these conditions, we have decided to concentrate on various foot pressure points in our body. We will be analyzing the positions and intensity of these pressure points and conclude our experiment by chalking out a graphical representation of all the data accumulated with the help of certain equipment. We will be asking the subject by giving instructions to place his or her feet on the multiple sensors insole normally (with no extra pressure from the subject’s side). Each sole sensor will send analog input data as the values of the applied foot pressure. Voltage outputs are collected from each input sensor. We will then compare the different output from different sensors with predetermined standard data (collecting from those who have normal Body Mass Index range). The comparative graph of the current subject and the standard data will then be able to help us to analyze where the disease condition is taking place. Key Words: Foot pathology, foot pressure points, lower-limb asymmetry, sole sensor, body mass index range.

Autoencoder Quasi-Recurrent Neural Networks for Remaining Useful Life Prediction of Engineering Systems

Remaining useful life (RUL) prediction is a key solution to improve the reliability, availability, and maintainability of engineering systems. Long short-term memory (LSTM) and convolution neural networks (CNN) are the current hotspots in the field of RUL prediction. However, the LSTM-based prognostic approach has a slow loop step to process large-scale time-series data since the dependence of the data processing process at each time on the output of the previous time limits parallelism, and the CNN-based prognostic approach is not fit for time-series data although it can process the data in parallel. In this article, a new autoencoder quasi-recurrent neural networks (AEQRNN) based prognostic approach is proposed for RUL prediction of the engineering systems. The AEQRNN contains convolution components that can process input data in parallel, and pooling components which has two LSTM-like gate structures to process time-series data. In addition, the AEQRNN can automatically extract hidden features from monitoring signals without manual feature design. The effectiveness of the proposed prognostic approach is validated by three prognostic benchmarking datasets, including a turbofan engine dataset, a rolling bearing dataset, and a machining tool dataset. Experimental results demonstrate that this approach has both superior prognostic performance and training speed in comparison with other kinds of recurrent-neural-network-based approaches and various state-of-the-art approaches in the recent literature.

Li memristor-based MOSFET synapse for linear I–V characteristic and processing analog input neuromorphic system

In this research, we propose a method that can significantly improve the linearity of current–voltage characteristics (L–IV) of synapse devices. Considering that analog input data are dependent on the L–IV, synapse devices having non-linear current–voltage characteristics can result in drastic conductance variations during inference operations. It means that the L–IV is one of the key parameters in the synapse device. To improve the L–IV, a triode region of a metal oxide semiconductor field effect transistor (MOSFET) was utilized with a Li-ion-based memristor as a gate voltage divider, which results in gradual channel conductance changes (analog synaptic weights). The channel conductance of the MOSFET can be selectively controlled based on Li-ion intercalation and de-intercalation. A notably improved L–IV and analog synaptic weights were achieved, which enhanced the MNIST data set recognition accuracy from 35.8% to 92.03%.

Spiking Neural Networks With Time-to-First-Spike Coding Using TFT-Type Synaptic Device Model

In hardware-based spiking neural networks (SNNs), the conversion of analog input data into the arrival time of an input pulse is regarded as a good candidate for the encoding method due to its bio-plausibility and power-efficiency. In this work, we trained an SNN encoded by time to first spike (TTFS) and performed an inference process using the behavior of the fabricated TFT-type flash synaptic device. The exponentially decaying synaptic current model required in the inference process was implemented by reading devices in the subthreshold region using triangle pulses. In a high-level system simulation, the TTFS-SNN (two-layer MLP with 512 hidden neurons) reached a high accuracy of 97.94%. Compared to conventional rate-encoded SNNs, TTFS-SNN made 2.9 times faster judgment and consumed ~10 times less energy in the inference process. Additionally, to use the network in a more stable condition, we propose a method to operate it using a rectangle pulse in the saturation region of the synaptic device. The distortion caused by this approximation was minimized by shortening the pulse width. As a result, the modified inference system showed an accuracy of 97.36%, and the prediction time and energy consumption were reduced 3.97- and 83.04-times when compared to those of the rate-SNN. Finally, we analyzed the sensitivity of the network performance due to unexpected issues that may occur in the hardware system and thus explained the competitiveness of the proposed synaptic behavior in the saturation region.

Fluidization Dynamics of Hydrophobic Nanosilica with Velocity Step Changes

Nanosilica is widely used in various applications, with its market expected to grow over USD 5 billion by 2025. The fluidized bed technology, owing to its intimate contact and efficient mixing of phases, is ideally suited for the large scale processing of powders. However, the bulk processing and dispersion of ultrafine nanosilica using the fluidized bed technology are critically affected by the interparticle forces, such that the hydrophilic nanosilica shows agglomerate bubbling fluidization (ABF), while the hydrophobic nanosilica undergoes agglomerate particulate fluidization (APF). This study carried out a detailed investigation into the fluidization hydrodynamic of the hydrophobic nanosilica by monitoring the region-wise dynamics of the fluidized bed subjected to a regular step change of fixed duration in the gas velocity. The gas flow was controlled using a mass controller operated with an analog output signal from a data acquisition system. The analog input data were acquired at the sampling rate of 100 Hz and analyzed in both time and temporal frequency domains. The effect of velocity transients on the bed dynamics was quickly mitigated and appeared as lower frequency events, especially in regions away from the distributor. Despite the apparent particulate nature of the fluidization, strong hysteresis was observed in both pressure drop and bed expansion. Moreover, the fully fluidized bed’s pressure drop was less than 75% of the theoretical value even though the bed appeared to free from non-homogeneities. Key fluidization parameters, e.g., minimum fluidization velocity (Umf) and the agglomerate size, were evaluated, which can be readily used in the large scale processing of nanosilica powders using fluidized bed technology.

USB Transceiver With a Serial Interface Engine and FIFO Queue for Efficient FPGA-to-FPGA Communication

This paper presents a universal serial bus (USB) transceiver with a serial interface engine (SIE) and an asynchronous first-in first-out (FIFO) queue for packet transformation and data transmission in field-programmable gate array (FPGA)-to-FPGA communication. The SIE block receives the data to be transmitted from the central processing unit of a PC and transfers those data to the universal transceiver macrocell interface, which handles data serialization and deserialization, bit stuffing, clock recovery, and clock synchronization. An asynchronous FIFO queue of 2 kilobits is designed to guarantee correct communication between two FPGA development boards. A parallel-in serial-out block converts parallel input data into serial data. A product identification (PID) check block determines whether the serial data are in the USB packet format. The cyclic redundancy check (CRC) checksums, namely CRC5 and CRC16, are presented with data check statements. After passing through the NRZI decoder, bit-unstuffing, PID check, and CRC16 blocks, the received serial data are converted into parallel output data by using a serial-in parallel-out block. The FPGA-to-FPGA communication design operates correctly. An application-specific integrated circuit (ASIC) of the USB transceiver is implemented using TSMC 0.18-μm CMOS technology. The gate counts, power consumption, operating frequency, and chip area of the ASIC are 14,547, 2.6742 mW, 50 MHz, and 0.7 × 0.67 mm 2 , respectively, at a supply voltage of 1.8 V and total pin number of 38.

Komunikasi Suara Sinyal Digital Dengan Transmisi Frekuensi 2,4 Ghz

The limitations of developing high-tech communication systems cause the area of people who can use this service to be uneven. One technology that can be used for areas not yet reached by this high-tech communication service is to use radio communication technology. Today radio communication technology continues to develop and produce an increasingly limited frequency spectrum. One way to improve the efficient use of available frequency spectrums is the transition from analog technology to digital technology. A very significant benefit in the use of digital technology is to save the use of radio frequency spectrum bandwidth with signal compression techniques. One device that still uses analog technology is a handy talky (HT). In addition to the lack of frequency spectrum efficiency, HT technology still requires a radio station license (ISR) for its use. This experiment designed a two-way digital audio communication system that was transmitted using the NRF24L01 radio frequency transceiver module on the 2.4Ghz frequency. Analog input data from the microphone will be converted into digital data through the ADC (Analog to Digital Converter) process using a microcontroller and the digital data that will be sent is first digitally modulated using GFSK modulation then transmitted digitally. On the other hand data that already contains voice information received again by another NRF24L01 transceiver is received by the Arduino microcontroller and then formed into a PWM signal (pulse width modulation) and then released to the speaker. So the method of using digital transmission can produce efficiencies in the frequency spectrum.

Integrated Exploration Methodology for Data Interleaving and Data-to-Memory Mapping on SIMD Architectures

This work presents a methodology for efficient exploration of data interleaving and data-to-memory mapping options for Single Instruction Multiple Data (SIMD) platform architectures. The system architecture consists of a reconfigurable clustered scratch-pad memory and a SIMD functional unit, which performs the same operation on multiple input data in parallel. The memory accesses contribute substantially to the overall energy consumption of an embedded system executing a data intensive task. The scope of this work is the reduction of the overall energy consumption by increasing the utilization of the functional units and decreasing the number of memory accesses. The presented methodology is tested using a number of benchmark applications with holes in their access scheme. Potential gains are calculated based on the energy models, both for the processing and the memory part of the system. The reduction in energy consumption after efficient interleaving and mapping of data is between 40% and 80% for the complete system and the studied benchmarks.

Bio-Inspired Temporal-Decoding Network Topologies for the Accurate Recognition of Spike Patterns

In this paper will be presented simple and effective temporal-decoding network topologies, based on a neuron model similar to the classic Leaky Integrate-and-Fire, but including the spike latency effect, a neuron property able to take into account that the firing of a given neuron is not instantaneous, but it occurs after a continuous-time delay depending on the inner state. These structures are able to detect spike sequences composed of pulses belonging to neuron ensembles, exploiting basic biological neuron mechanisms. According to the biological counterpart, with these structures is possible to achieve a high temporal accuracy, but also deal with the natural variability present in spike trains. In addition, the connection of these neural structures at a higher level make possible to afford some pattern recognition problems, operating a distributed and parallel input data processing.

Automated Home Appliances Control using Embedded Web Server

In modern construction in industrialized nations, most homes have been wired for TV, lights and fans etc... Many household tasks were automated by the development of specialized automated appliances. In this project we are going to create the embedded web server so that we can control the electrical devices through online by using either computer or by using smart phone. The purpose of this project is to design a control system that able to control a system device remotely from distance and monitoring condition of the system in real-time as well. This project shows how to set up an Arduino with Ethernet shield as a web server. The web servers in this Project are used to serve up web pages that can be accessed from a web browser and allows our hardware to be controlled from web browser. Starting from basic, our example for this project is simple. We want to access our device by switching ON-OFF LED and monitor analog input data acquisition from web server, which are the computer and Arduino connected to the same network.

차량 통신 기술을 위한 OFDM 모듈레이션의 64-비트 스크램블러 설계

WAVE 시스템은 IEEE 802.11p표준으로 지능형 교통시스템 서비스에 응용되는 새로운 개념 및 차량 통신 기술이다. 또한 WAVE 시스템은 도로상의 트래픽의 효율과 안전을 높인다. 그러나 WAVE 시스템의 OFDM 모듈레이션에서 스크램블러 비트 연산 알고리즘은 하드웨어나 소프트웨어 측면에서 병렬 처리가 불가능하므로 효율성이 떨어지게 된다. 본 논문에서는 스크램블러의 비트 연산으로 64비트 행렬 테이블을 구성하는 알고리즘과 64비트 행렬 테이블과 입력 데이터를 병렬 연산하는 알고리즘을 제안하였다. 제안한 알고리즘은 64비트 행렬 테이블을 적용하여 실행한 결과 비트연산 스크램블러보다 1회와 10000회 처리 속도는 약 40.08%-40.27%가 향상되고, 초당 처리 횟수는 468.35회 더 수행할 수 있고, 32비트 스크램블러보다 1회와 10000회 처리 속도는 약 7.53%-7.84%가 향상되고, 초당 처리 횟수는 91.44회 더 수행할 수 있다. 따라서 64비트로 연산하는 스크램블러 알고리즘은 64비트를 처리할 수 있는 CPU를 사용한다면 32비트 스크램블러보다 40% 이상 성능을 향상시킬 수 있다. WAVE(Wireless Access for Vehicular Environment) is new concepts and Vehicles communications technology using for ITS(Intelligent Transportation Systems) service by IEEE standard 802.11p. Also it increases the efficiency and safety of the traffic on the road. However, the efficiency of Scrambler bit computational algorithms of OFDM modulation in WAVE systems will fall as it is not able to process in parallel in terms of hardware and software. This paper proposes an algorithm to configure 64-bits matrix table in scambler bit computation as well as an algorithm to compute 64-bits matrix table and input data in parallel. The proposed algorithm on this thesis is executed using 64-bits matrix table. In the result, the processing speed for 1 and 1000 times is improved about 40.08% ~ 40.27% and processing rate per sec is performed more than 468.35 compared to bit operation scramble. And processing speed for 1 and 1000 times is improved about 7.53% ~ 7.84% and processing rate per sec is performed more than 91.44 compared to 32-bits operation scramble. Therefore, if the 64 bit-CPU is used for 64-bits executable scramble algorithm, it is improved more than 40% compare to 32-bits scrambler.

Giga bit per second Differential Scheme for High Speed Interconnect

The performance of many digital systems today is limited by the interconnection bandwidth between chips. Although the processing performance of a single chip has increased dramatically since the inception of the integrated circuit technology, the communication bandwidth between chips has not enjoyed as much benefit. Most CMOS chips, when communicating off-chip, drive unterminated lines with full-swing CMOS drivers. Such full-swing CMOS interconnect ring-up the line, and hence has a bandwidth that is limited by the length of the line rather than the performance of the semiconductor technology. Thus, as VLSI technology scales, the pin bandwidth does not improve with the technology, but rather remains limited by board and cable geometry, making off-chip bandwidth an even more critical bottleneck. In order to increase the I/O Bandwidth, some efficient high speed signaling standard must be used which considers the line termination, signal integrity, power dissipation, noise immunity etc In this work, a transmitter has been developed for high speed offchip communication. It consists of low speed input buffer, serializer which converts parallel input data into serial data and a current mode driver which converts the voltage mode input signals into current over the transmission line. Output of 32 low speed input buffers is fed to two serializer, each serializer converting 16 bit parallel data into serial data stream. Output of two serializers is fed to LVDS current mode driver. The serial link technique used in this work is the time division multiplex (TDM) and point-to-point technique. It means that the low-speed parallel signals are transferred to the high-speed serial signal at the transmitter end and the high-speed serial signal is transferred to the low-speed parallel signals at the receiver end. Serial link is the design of choice in any application where the cost of the communication channel is high and duplicating the links in large numbers is uneconomical.

Interview

The most compact data sorter so far has been proposed by researchers at the Federal University of Technology of Paraná in Brazil. Professor Volnei Pedroni tells us more about the research behind his team's Letter ‘Panning sorter: an approach to the design of minimal-hardware parallel-input data sorters’ on page 1262.

Joint Multilevel Turbo Equalization and Continuous Phase Frequency Shift Keying

A novel type of turbo coded modulation scheme, called multilevel turbo coded-continuous phase frequency shift keying (MLTC-CPFSK), is designed to improve the overall bit error rate (BER) and bandwidth efficiency. Then, this scheme is combined with a new double decision feedback equalizer (DDFE) to remove the interference and to enhance BER performance for the intersymbol interference (ISI) channels. The entire communication scheme is called multilevel turbo equalization-continuous phase frequency shift keying (MLTEQ-CPFSK). In these schemes, parallel input data sequences are encoded using the multilevel scheme and mapped to CPFSK signals to obtain a powerful code with phase continuity over the air. The performances of both MLTC-CPFSK and MLTEQ-CPFSK systems were simulated over nonfrequency and frequency-selective channels, respectively. The superiority of the two level turbo codes with 4CPFSK modulation is shown against the trellis-coded 4CPFSK, multilevel convolutional coded 4CPFSK, and TTCM schemes. Finally, the bit error rate curve of MLTEQ-CPFSK system over Proakis B channel is depicted and ISI cancellation performance of DDFE equalizer is shown against linear and decision feedback equalizers.

Multilevel turbo coded–continuous phase frequency shift keying (MLTC–CPFSK)

In this paper, we introduce a Turbo coded modulation scheme, called multilevel turbo coded–continuous phase frequency shift keying (MLTC–CPFSK). The underlying basis of multilevel coding is to partition a signal set into several levels and to encode separately each level through the respective layer of the encoder. In MLTC–CPFSK, to provide phase continuity of the signals, turbo encoder and continuous phase encoder (CPE) are serially concatenated at the last level, while all other levels consist of only a turbo encoder. Therefore, the proposed system contains multiple turbo encoder/decoder blocks in its architecture. The parallel input data sequences are encoded by our multilevel scheme and mapped to CPFSK signals. Then, for the purpose of performance analysis, these modulated signals are passed through AWGN and fading channels. At the receiver side, the input sequence of the first level is estimated by the first turbo decoder block. Subsequently, the other input sequences of other levels are computed using the estimated input bit streams of the respective previous levels. Simulation results are drawn for 4-ary CPFSK two level and 8-ary CPFSK three level turbo codes over AWGN, Rician, and Rayleigh channels for three iterations while frame sizes are chosen as 100 and 1024. It is concluded that satisfactory performance is achieved in MLTC–CPFSK systems for all SNR values in various fading environments.

Performance of multilevel‐turbo codes with blind/non‐blind equalization over WSSUS multipath channels

AbstractIn this paper, in order to improve error performance, we introduce a new type of turbo codes, called ‘multilevel‐turbo codes (ML‐TC)’ and we evaluate their performance over wide‐sense stationary uncorrelated scattering (WSSUS) multipath channels. The basic idea of ML‐TC scheme is to partition a signal set into several levels and to encode each level separately by a proper component of the turbo encoder. In the considered structure, the parallel input data sequences are encoded by our multilevel scheme and mapped to any modulation type such as MPSK, MQAM, etc. Since WSSUS channels are very severe fading environments, it is needed to pass the received noisy signals through non‐blind or blind equalizers before turbo decoders. In ML‐TC schemes, noisy WSSUS corrupted signal sequence is first processed in equalizer block, then fed into the first level of turbo decoder and the first sequence is estimated from this first Turbo decoder. Subsequently, the other following input sequences of the frame are computed by using the estimated input bit streams of previous levels. Here, as a ML‐TC example, 4PSK 2 level‐turbo codes (2L‐TC) is chosen and its error performance is evaluated in WSSUS channel modelled by COST 207 (Cooperation in the field of Science & Technology, Project #207). It is shown that 2L‐TC signals with equalizer blocks exhibit considerable performance gains even at lower SNR values compared to 8PSK‐turbo trellis coded modulation (TTCM). The simulation results of the proposed scheme have up to 5.5 dB coding gain compared to 8PSK‐TTCM for all cases. It is interesting that after a constant SNR value, 2L‐TC with blind equalizer has better error performance than non‐blind filtered schemes. We conclude that our proposed scheme has promising results compared to classical schemes for all SNR values in WSSUS channels. Copyright © 2005 John Wiley & Sons, Ltd.

Performance of multilevel turbo codes with group partitioning over satellite channels

A new type of turbo codes called multilevel turbo codes (ML–TC) which employ a new partitioning technique (group partitioning) in order to improve channel error performance. The underlying basis for multilevel coding is partitioning a signal set into several levels and encoding each level separately through the respective layer of the encoder. Initial partitioning levels are very important for the performance of ML–TC schemes. Group partitioning maximises the Euclidean distance of these levels, and it provides additional bit error performance augmentation of 0.6 dB for the range of signal-to-noise ratio (SNR) under study. The ML–TC system contains multiple turbo encoder/decoder blocks in its architecture. The parallel input data sequences are encoded by the multilevel scheme and mapped to any modulation type, such as MPSK, MQAM, etc. Then, for the purpose of performance analysis, these modulated signals are passed through narrowband fading channels. At the receiver side, the input sequence of the first level is estimated by the first turbo decoder block. Subsequently, the other input sequences of other levels are computed using the estimated input bit streams of the respective previous levels. Following that process, the performance of the proposed system is investigated in various fading channels. As an example, 4-PSK two-level turbo codes are simulated over AWGN, Rician and Rayleigh channels for 100 and 256 frame sizes. ML–TC simulation results display coding gains of up to 4.5 dB, when compared to those of 8-PSK turbo trellis-coded modulation. Therefore, it is concluded that satisfactory performance is achieved in ML–TC systems for all SNR values in various fading environments.

A plug and play approach to data acquisition

Backplane buses are becoming a legacy for high-rate, high-volume data processing applications. Higher efficiency at lower cost is offered by the PCI bus technology, compared to crate-embedded processors. Becoming part of the plug and play domain of the host's operating system, no additional data transfer protocols are needed. We have combined PCI technology with high-density field-programmable gate array (FPGA) logic and common mezzanine standards on a flexible PCI card. First applications cover readout controllers for legacy bus protocols, high-speed link I/O and fast analog input data conversion. An FPGA with embedded PCI master/target core serves as a programmable interface between the PCI bus, mezzanine cards, and a local SDRAM. Adapter mezzanine cards, implemented according to the IEEE P1386 or similar common standards, are used for voltage level conversion, trigger interfacing or preprocessing. The application-dependent controller functions as well as SDRAM and PCI interfacing are handled by FPGA logic. A Linux driver was developed to achieve high bandwidth via CPU-initiated transfers. Control software for Windows and an interface for LabView target control and monitoring applications via graphical interfaces. First experience and applications are reported.

A parallel systolic array ASIC for real-time execution of the Hough transform

Many pattern recognition problems can be solved by mapping the input data into an n-dimensional feature space in which a vector indicates a set of attributes. One powerful pattern recognition method is the Hough transform. In reducing the n-dimensional feature space to two dimensions, the coordinate transform can be executed by a systolic array consisting of time-delay processing elements and adders. The application-specific integrated circuit (ASIC) implementation of the Hough transform as a systolic array for real-time recognition of curved tracks in multiwire drift chambers is presented. The array can handle 32 parallel input data streams. It mainly consists of 512 identical programmable processing elements. Sixteen histogram pixels in the feature space are produced in parallel per clock cycle. The ASIC is implemented in 0.6 /spl mu/m CMOS, two-metal layer technology (CUB) from Austria Micro Systems (AMS) and operates with a clock frequency of 100 MHz. The interconnectivity pattern of the processing elements required to initialize the chip according to the pattern recognition task is computed on the host computer using the Hough-transform equations. This pattern is then downloaded to the chip via the data input lines. The Hough-transform ASIC is suitable for a wide range of pattern recognition applications. The integrated circuit is a powerful building block for systems requiring real-time execution of the Hough transform.

A 10-Gb/s 16:1 multiplexer and 10-GHz clock synthesizer in 0.25-μm SiGe BiCMOS

A 10-Gb/s 16:1 multiplexer, 10-GHz clock generator phase-locked loop (PLL), and 6 /spl times/ 16 b input data buffer are integrated in a 0.25-/spl mu/m SiGe BiCMOS technology. The chip multiplexes 16 parallel input data streams each at 622 Mb/s into a 9.953-Gb/s serial output stream. The device also produces a 9.953-GHz output clock from a 622- or 155-MHz reference frequency. The on-board 10-GHz voltage-controlled oscillator (VCO) has a 10% tuning range allowing the chip to accommodate both the SONET/SDH data rate of 9.953 Gb/s and a forward error correction coding rate of 10.664 Gb/s. The 6 /spl times/ 16 b input data buffer accommodates /spl plusmn/2.4 ns of parallel input data phase drift at 622 Mb/s. A delay-locked loop (DLL) in the input data buffer allows the support of multiple input clocking modes. Using a clock generator PLL bandwidth of 6 MHz, the 9.953-GHz output clock exhibits a generated jitter of less than 0.05 UI/sub P-P/ over a 50-kHz to 80-MHz bandwidth and jitter peaking of less than 0.05 dB.