Input Data Bits Research Articles

Reconfiguration of PV array for improved performance under different partial shading conditions using Roulette Barrel Shifter approach

This article proposes an innovative reconfiguration technique called Roulette Barrel Shifter (RBS) for Total Cross Tied (TCT) connected PV arrays. Inspired by a spinning roulette wheel and the barrel shifter from digital signal processing, it shifts or rotates input data bits by a number of bits. Unlike other methods, RBS does not require advanced maximum power point tracking devices, sensors, or complex switching mechanisms, making it more cost-effective. Simulation studies on 9 × 9 and 10 × 10 PV arrays under Partial Shading (PS) conditions, as well as experimental validation on a 5 × 5 array, demonstrate that RBS increases power by up to 15.45 % compared to TCT. The algorithm is also tested for scalability and adaptability on a large solar plant (4 MW, 2175 V, 25 × 750 PV array). For the first time, the article introduces a unique wiring loss (WL) performance metric using the k-means algorithm. Based on this metric, RBS is shown to reduce WL by up to 6.98 % compared to other recently published methods. Comparative analysis reveals that RBS reduces mismatch loss (ML) by up to 61.41 % compared to TCT, establishing its superiority over existing dynamic reconfiguration approaches in both performance and efficiency across various scales of solar arrays.

Design and Implementation of Adaptive Universal Filtered Multi Carrier for 5G and Beyond

The current generation (5G) mobile communication system promises to accommodate a wide range of new applications and use scenarios, resulting in more flexible and unified connection. To satisfy the required criteria, the current waveform was replaced with new UF-OFDM, which combines the advantages of OFDM with enhanced spectral characteristics and greater resilience against time-frequency misalignments. However, its biggest disadvantage is the transmitter's computational complexity, which may be up to two hundred times that of OFDM if there is no reduction in complexity. The majority of current research on unique waveforms has focused on filter modification or performance enhancement strategies. UFMC with the use of adaptive filter (UFMC -FSK) is offered as a revolutionary technique in this study. The filter designed and used to transport information through the index modulation technique. As a result, each UF-OFDM sub band's used filter is chosen, so the data rate is enhanced according to a filter configured depending on original input data bits. The combined Maximum-likelihood (ML) decision metric for each sub band that is calculated at the receiver. Each sub band has a filter as well as data symbols that provide the minimal metric for making decisions are discovered. Furthermore, the bit error rate and power spectrum density are enhanced over the UF-OFDM technique, however there is some trade-off. Overall, the proposed system outperform typical UF-OFDM. Matlab simulations are used to assess the performance of the Adaptive UFMC system.

FT-EALU: fault-tolerant arithmetic and logic unit for critical embedded and real-time systems

This paper presents a fault-tolerant ALU (“FT-EALU”) based on time redundancy and reward/punishment-based learning approaches for real-time embedded systems that face limitations in hardware and power consumption budgets. In this method, operations are diversified to three versions in order to correct permanent faults along with the transient ones. The diversities of versions considered in FT-EALU are provided by lightweight modifications to differentiate them and clear the effect of permanent faults. Selecting lightweight modifications such as shift and swap would avoid high timing overhead in computation while providing significant differences which are necessary for fault detection. Next, the replicated versions are executed serially in time, and their corresponding results are voted based on the derived learned weights. The proposed weighted voting module generates the final output based on the results and their weights. In the proposed weighted voting module, a reward/punishment strategy is employed to provide the weight of each version of execution indicating its effectiveness in the final output. To this aim, in the method defined for each version of execution, a weight is defined according to its correction capability confronting several faulty scenarios. Thus, this weight defines the reliability of the temporal results as well as their effect on the final result. The final result is generated bit by bit based on the weight of each version of execution and its computed result. Based on the proposed learning scheme, positive or negative weights are assigned to execution versions. These weights are derived in bit level based on the capability of execution versions in mitigating permanent faults in several fault injection scenarios. Thus, our proposed method is low cost and more efficient compared to related research which are mainly based on information and hardware redundancy due to employing time redundancy and static learning approach in correcting permanent faults. Several experiments are performed to reveal the efficiency of our proposed approach based on which FT-EALU is capable of correcting about \(84.93\%\) and \(69.71\%\) of permanent injected faults on single and double bits of input data.

Adaptive Synapse Arrangement in Cortical Learning Algorithm

The cortical learning algorithm (CLA) is a time-series data prediction method that is designed based on the human neocortex. The CLA has multiple columns that are associated with the input data bits by synapses. The input data is then converted into an internal column representation based on the synapse relation. Because the synapse relation between the columns and input data bits is fixed during the entire prediction process in the conventional CLA, it cannot adapt to input data biases. Consequently, columns not used for internal representations arise, resulting in a low prediction accuracy in the conventional CLA. To improve the prediction accuracy of the CLA, we propose a CLA that self-adaptively arranges the column synapses according to the input data tendencies and verify its effectiveness with several artificial time-series data and real-world electricity load prediction data from New York City. Experimental results show that the proposed CLA achieves higher prediction accuracy than the conventional CLA and LSTMs with different network optimization algorithms by arranging column synapses according to the input data tendency.

An Enhanced Low Power Dual Data Injection Technique for Coarse - Grained Reconfigurable Architecture

oarse-gr ained reconfigurable architectures (CGRA) having a well-organized, more efficient configurable array of processing unit and high speed cache unit. The processing unit performs required arithmetic and logic operations. Now a day’s video processing applications power consumption plays an important role. We propose Double Data Rate Synchronous Memory architecture can address and reduce the power consumption caused by reconfiguration. An input data bits are injecting on the data bus in the interval of low to high and high low clock period. All modules have been designed and implemented in vertex using behavioral level with VHDL coding and to Simulate in Xilinx ISE navigator.

Writing 10 Gb/s Data Bits With Addressing Using External Cavity-Based SMFP-LDs

Memory accessing is one of the challenging issues for utilizing the improvements in processor speed. Due to the rapid enhancement on processor speed compared to the memory accessing technique, the gap between the memory accessing and processor speed is rapidly widening. Hence, a new technique to address this issue needs to be devised. In this paper, we experimentally demonstrate the complete scheme of wavelength division multiplexing enabled memory write operation in the desired memory location using single mode Fabry–Perot laser diodes (SMFP-LDs). For a proof of concept, we demonstrate writing a stream of data bits at 10 Gb/s data rate in a memory unit that consists of four single bit set–reset (SR) latches with a unique address. The input data bits are stored in the respective latch of the memory bank in accordance with the address bit set along with a write instruction. A higher order of memory units with address decoding can be realized by increasing the higher order of decoder and the memory units. The observed optical domain waveforms at the respective nodes of each block, eye diagram, SNR, and bit error rate (BER) prove the verification of writing input data to the desired memory locations using SMFP-LDs. We observed an extinction ratio of more than 12 dB, no noise floor at the BER of 10−12, and a maximum power penalty of about 2.5 dB in the proposed scheme.

Region Secure and Pattern Based Alternate 2B-3C Steganography Approach for Data Security in Color Images

Background and Objective: The public and group communication carried out in the social, cloud, and mobile networks suffer from unauthorized users. The data security is required for secure authentication, monetary transactions and other sensitive information. The steganography methods empower the user with invulnerable communication in public domain. In this paper, a region secure and pattern based alternate 2B-3C (2Bit-3Channel) Steganography method is proposed to improve the content reliability and data security. Methods: In this method, the cover pixels are retrieved by applying the spiral rectangular pattern over the cover image. This spiral pattern also secures the core content region and the pixels from the core ROI (Region of Interest) is used as a cover only for larger size secret information. In this proposed steganography method, two channels are considered alternatively based on the defined rules. The LSB (Least Significant Bit) of both channels is XOR with input data bits and key to perform data hiding. The method is applied on real time color images taken from COREL and USC-SIPI-ID. The evaluation of proposed steganography approach is done using MSE (Mean Square Error), PSNR (Peak Signal-to-Noise Ratio), BER (Bit Error Rate), NCC (Normalized Cross Correlation) and SSIM (Structural Similarity Index Matrix). Result: The comparative results are generated for 50 real time images against the existing LSB (Least Significant Bit), LSBM (Least Significant Bit Modulation), LSBMR (Least Significant bit Matched Revisited), SCC (Stego Color Cycle), SHSI (Simple Hue-Saturation-Intensity), HIS-MLSB(Simple Hue-Saturation-Intensity-Modified LSB) and IMMEA(Iterative Magic Matrix Encryption Algorithm) methods. Conclusion: The experimentation results verified that the proposed 2B-3C approach improved the data hiding in qualitative and quantitative aspects.

Simulation and Spectral Analysis of the Scrambler for 56Kbps Modem

Scrambler is a device that performs one-to-one mapping between input data bits and channel codes. It is used in synchronous data communication systems to retrieve timing information from the received data i.e. to aid synchronization between two modems. Present paper deals with the computer-aided simulation and spectral analysis of the scrambler to be used in 56Kbps voice-band modem. Matlab has been used for simulation and pre-spectral analysis including power spectral density, cross-correlation and auto-correlation. Implementation of scrambler has been done on Texas Instrument's TMS320C50 digital signal processor (DSP) and post- spectral analysis has been performed using Signalogic DSP software. Simulated and practical results have been found identical, which ensures the successful implementation of scrambler.

A 12‐bit segmented resistor‐capacitor digital‐to‐analog converter for a display driver IC of a large TFT‐LCD panel system

Abstract— A 12‐bit segmented R‐C DAC to support a linear gamma curve has been proposed and fabricated in a 720‐channel LCD source driver with a 16‐V 1‐poly 3‐metal high‐voltage CMOS process. The proposed DAC has a global resistor string and sample‐and‐hold buffers. A MSB voltage selected by the upper 6 bits of input data and a LSB voltage selected by the lower 6 bits of input data are summed by using a sample‐and‐hold operation with offset cancellation in the proposed DAC. The measured DNL was less than 0.3 LSB, and the output voltage deviation was less than 3 mV in all gray levels. Although two sample‐and‐hold buffers were adopted to operate alternatively, the die size was as small as 24.9 mm2, which was only an 8.3% increase compared to that of a conventional 8‐bit 720‐channel source driver. Because of its good performance with small area, the proposed DAC can be a good low‐cost solution for a 10‐bit TV system.

Molecular logic gates based on pentacyanoferrate complexes: from simple gates to three-dimensional logic systems.

The article presents new aspects of reactivity of two pentacyanoferrates: [Fe(CN)5NO]2- and [Fe(CN)5N(O)SR]3-. The dependence of thermodynamic functions on cations was found for the reaction between nitroprusside and thiolate. The thermodynamic data are interpreted in terms of ion pairing and changes in the solvation shell of the cations. It was found that the reaction enthalpies and entropies depend strongly on the cation radius. The reaction volume in turn is strongly affected by the structure and properties of the hydration shell. Careful data analysis allowed the contribution of partial cation dehydration to the total reaction volume to be determined. The experimental results were also interpreted in terms of chemical logic gates. Complex logic systems were built from a number of cells containing a switching compound arranged in different geometric patterns. Increasing the dimensionality of these arrangements leads to really complex logic systems containing up to 20 AND and OR logic gates. The system is capable of processing up to 16 bits of input data.

Low‐temperature poly‐Si TFT‐LCD with an integrated analog circuit

Abstract—We have developed a 6‐bit D/A converter and amplifier integrated low‐temperature poly‐Si TFT‐LCD in which an integrated signal‐line driver is driven by a 5‐V power supply. We have employed a D/A converter including a new capacitor array and an original amplifier comprised of serially connected comparators to achieve high accuracy. The D/A converter performs gamma correction using upper significant bits of input data. Control signals for these circuits were generated by the integrated timing circuit. These advances in integration have been achieved for the first time using 3‐μm design rule and improved LTPS TFT technologies and provide an advanced display system with lower power consumption, smaller module size, and higher durability.

4739505 IC chip error detecting and correcting apparatus with automatic self-checking of chip operation

Error detecting and correcting operations for a plurality of input bits comprised of input data bits and associated check bits are implemented using two IC chips in order to overcome chip output limitations. In addition, redundancies derived from the use of two IC chips are employed to provide automatic self-checking of the detecting operation of each chip. The use of two identical IC chips for this purpose is made possible by employing a specially chosen inversely symmetrical Hamming code and by wiring the input data bits and the input check bits in an inverse manner with respect to the input terminals of the two IC chips. As a result, even though each IC chip performs the same error detecting and correcting operations, it does so inversely with respect to the input data bits and the input check bits so that each IC chip is able to provide one-half of the required output bits.