Input Compression Point Research Articles

An-QNA: An Adaptive Nesterov Quasi-Newton Acceleration-Optimized CMOS LNA for 65 nm Automotive Radar Applications.

An adaptive Nesterov quasi-Newton acceleration (an-QNA)-optimized low-noise amplifier (LNA) is proposed in this paper. An optimized single-ended-to-differential two-stage LNA circuit is presented. It includes an improved post-linearization (IPL) technique to enhance the linearity. Traditional methods like conventional quasi-Newton (c-QN) often suffer from slow convergence and the tendency to get trapped in local minima. However, the proposed an-QNA method significantly accelerates the convergence speed. Furthermore, in this paper, modifications have been made to the an-QNA algorithm using a quadratic estimation to guarantee global convergence. The optimized an-QNA-based LNA, using standard 65 nm CMOS technology, achieves a simulated gain of 17.5 dB, a noise figure (NF) of 3.7 dB, and a 1 dB input compression point (IP1dB) of -13.1 dBm. It is also noted that the optimized LNA achieves a measured gain of 12.9 dB and an NF of 4.98 dB, and the IP1dB is -17.8 dB. The optimized LNA has a chip area of 0.67 mm2.

(Digital Presentation) Sub-THz Front Ends for Future Communication and Sensing Technologies in 130nm Sige Bicmos Technology

Introduction: Beyond the-5G technologies are targeting the available bandwidth (BW) in the D-band and J-band. This promises for very high speed communication and sensing accuracy. Although the advantages of operating beyond 100 GHz from the application point of view, it requires a lot of research and development to design a reliable and power efficient chipsets. In this presentation we will go through the design of wideband 240 GHz transmitter (Tx) and receiver (Rx). Firstly an overview about the link budget analysis will be given, then the design of the local carrier signal generator will be discussed. The wideband Txs and Rxs are to be presented with frequency channelizing concept. At the end the results of the wireless links will be demonstrated. Link Budget Analysis: Operating at sub-THz frequencies approaching the transistor fT put a lot of constraints on the system link budget. The elevated noise figure together with the limited maximum Pout of the transistors lead to solutions which might be limited in BW or power efficiency. Hence the design architecture need to be optimized taking into account the elevated power consumption and heat dissipation. Carrier Generation: Several approaches could be followed to generate the sub-THz carrier frequency. For a power efficient solution the fundamental oscillators promise for a power efficient solution but with limited phase noise performance and tuning range. Such a solution is more common for imaging systems operating at a single frequency. In order to achieve wider tuning ranges for multi-channel scenario or FMCW radar systems, the frequency multiplication chains are common, whereas the multiplication factor depends on the system parameters. Sub-THz Rx: Different approaches were followed to realize a wideband sub-THz Rx. For some technologies the transistors ft does not promise the realization of low noise amplifiers (LNA) with reasonable noise figure, gain and BW. Hence the mixer first approach were followed trying to optimize the noise figure of the down conversion mixer as much as possible. This also enhances the input compression point (IP1dB) of the Rx which is better for monostatic radar applications. On the other hand, if the technology in use allows the development of well performing LNA’s, the LNA first approach was followed to enhance the all over NF of the receiver and ease the implementation of IQ Rxs. In our work an LNA was implemented followed by IQ downconversion mixers and baseband chain as presented in [3]. Sub-THz Tx: The Tx main challenging performance parameter in the sub-THz frequency range is to achieve high output compression point across the required BW with as high efficiency as possible. Increasing the power handling capabilities of the power amplifiers (PA) by increasing the transistors sizes of the output stages, leads to low output impedance and hence higher impedance transformation ratios for the matching structures and eventually narrow band designs. Hence the power combining architectures were proposed as an alternative to increase the output power either by combining on-chip or combining in air. In this work a fully integrated IQ Tx is to be presented with on-chip LO chain and 4-way power combined power amplifier. Baseband Signal Generation and Processing The baseband topology depend on the application. For mobile communication or localization use cases a wideband channels are not available directly from the digital processors, a kind of channel bonding is required either in the digital domain or in the analog domain. As a proof of concept we present here 3-IQ frequency interleaving combiner. Wireless Link Demonstrator Two demonstrators are to be presented. The first demonstrator is transmitting a broadband IQ signal generated from an arbitrary wave generator wirelessly utilizing an IQ 240GHz Tx and Rx. Data rates up to 100 Gbps were demonstrated across a 1m of wireless link. The second demonstrator includes the implementation of 3-channel IQ channelizer to create the complex modulated signal at several intermediate frequencies (IFs) and then upconverted to the 240GHz carrier signal. On the Rx side the de-channelizer convert the down modulated signal to three IQ channels. Data rates up to 8Gbps were demonstrated wirelessly with the channelization with potential of further enhancements for more channels integration. Outlook The future of the sub-THz wireless links for high speed communication and localizations goes towards implementing phased array and MIMO systems. This requires the research community to develop novel architectures to develop large scale arrays with acceptable power consumptions and suitable packaging solution. On the baseband side also the channel bonding solutions are still in an early stage, requiring more work to bond modularly larger number of channels.

Predicting the Performance of a 26 GHz Transconductance Modulated Downconversion Mixer as a Function of LO Drive and DC Bias

The dependency of RF performance on the local oscillator (LO) drive amplitude and DC bias is an important topic for RF mixers, especially as carrier frequency increases and generation of RF power thus becomes more complex. The prediction of mixer performance, without initial reliance on full circuit simulations, can provide important insights. In this work, mathematical models without the prior use of circuit simulation are developed, leading to a strategy to predict the conversion gain (Gc), DC current, 1 dB input compression point (IP1dB) and third order input intercept point (IIP3) for a SiGe bipolar transistor transconductance mixer. The models show the possibility to trade-off LO RF power and DC bias to achieve a desired performance. The concepts allow a prediction of the necessary DC bias required to support a chosen LO level and desired conversion transconductance or linearity. The mathematical model results, circuit simulation results, and measured hardware results from a 26 GHz prototype of a single-ended mixer are presented and compared, showing good agreement. In a lab-measured example, LO power reduction from +10 dBm to +3 dBm resulted in only a 1 dB reduction in conversion gain, by modifying the DC bias as predicted. The peak conversion gain predicted by the models is within 2.0 dB of circuit simulation and 2.5 dB of measured PCB results. The RMS error for predicted DC current, compared to circuit simulation, is 1.9 mA or better.

A Sub-6G SP32T Single-Chip Switch with Nanosecond Switching Speed for 5G Applications in 0.25 μm GaAs Technology

This paper presents a single-pole 32-throw (SP32T) switch with an operating frequency of up to 6 GHz for 5G communication applications. Compared to the traditional SP32T module implemented by the waveguide package with large volume and power, the proposed switch can significantly simplify the system with a smaller size and light weight. The proposed SP32T scheme utilizing tree structure can dramatically reduce the dc power and enhance isolation between different output ports, which makes it suitable for low-power 5G communication. A design methodology of a novel transmission (ABCD) matrix is proposed to optimize the switch, which can achieve low insertion loss and high isolation simultaneously. The average insertion loss and the isolations are 1.5 and 35 dB at 6 GHz operating frequency, respectively. The switch exhibits the measured input return loss which is better than 10 dB at 6 GHz. The 1 dB input compression point of SP32T is 15 dBm. The prototype is designed in 5 V 0.25 μm GaAs technology and occupies a small area of 12 mm2.

An Integrated 65-nm CMOS SOI Ka-Band Asymmetrical Single-Pole Double-Throw Switch Based on Hybrid Couplers

This letter presents the design of an asymmetrical Ka-band single-pole double-throw (SPDT) switch, based on two integrated hybrid couplers. The principle of operation of this switch and its two asymmetrical receiving (Rx) and transmitting (Tx) states are detailed. The circuit theory is supported by the implementation of a demonstrator using an advanced integrated technology: 65-nm substrate on insulator (SOI) CMOS from STMicroelectronics. To the author's best knowledge, it is the first implementation of such topology using an integrated CMOS technology. The demonstrator is designed considering a system-level tradeoff between the two states, in order to implement 28-GHz duplexers for 5G front-end modules (FEMs). The Rx state exhibits 1.9 dB of insertion loss, 24 dB of isolation and a 1 dB input compression point of 17.5 dBm, whereas the Tx state has 2.9 dB and 35 dB of insertion loss and isolation, respectively. Besides, the gain compression in the Tx state is lower than 0.3 dB, considering an input power of 18 dBm.

2.3–21 GHz broadband and high linearity distributed low noise amplifier

This paper focuses on the design of a 2.3–21 GHz Distributed Low Noise Amplifier (LNA) with low noise figure (NF), high gain (S21), and high linearity (IIP3) for broadband applications. This distributed amplifier (DA) includes S/C/X/Ku/K-band, which makes it very suitable for heterodyne receivers. The proposed DA uses a 0.18 μm GaAs pHEMT process (OMMIC ED02AH) in cascade architecture with lines adaptation and equalization of phase velocity techniques, to absorb their parasitic capacitances into the gate and drain transmission lines in order to achieve wide bandwidth and to enhance gain and linearity. The proposed broadband DA achieved an excellent gain in the flatness of 13.5 ± 0.2 dB, a low noise figure of 3.44 ± 1.12 dB, and a small group delay variation of ±19.721 ps over the range of 2.3–21 GHz. The input and output reflection coefficients S11 and S22 are less than −10 dB. The input compression point (P1dB) and input third-order intercept point (IIP3) are −1.5 dBm and 11.5 dBm, respectively at 13 GHz. The dissipated power is 282 mW and the core layout size is 2.2 × 0.8 mm2.

A wideband blocker-resilient direct delta sigma receiver with selective input-impedance matching

This paper presents a wideband blocker-tolerant direct varDelta varSigma receiver (DDSR). Blockers are attenuated through selective input impedance matching and reduced gain design. The selective input impedance profile provides a low impedance at blocker frequencies enabling blocker attenuation, while the in-band impedance is boosted to matched condition through an up-converted positive feedback from the DDSR output. In addition, with the help of reduced gain design, near band blocker gain is minimized, further improving the blocker resilience. The receiver is designed for configurable operation from 0.7–2.7 GHz and a baseband bandwidth of 10 MHz. Simulated in a 28 nm technology, the DDSR demonstrates a maximum noise figure of 6.2 dB, and achieves a peak SNDR of 53 dB with an out-of-band 1 dB input compression point of -,11 dBm at a 100 MHz offset.

A 160-GHz system in package for short-range mm-wave applications

This paper proposes a fully integrated 160-GHz transmitter and receiver in package for millimeter-wave applications. The monolithic integrated circuits were designed with a harmonic approach and were fabricated using a SiGe:C HBT production technology with an fTand fmaxof 170 and 250 GHz, respectively. The manufactured 2006 × 1865 µm2bare dies were integrated in 6 × 6 mm2embedded wafer level ball grid array packages, where they were interconnected with highly directional antennas built on the redistribution layer of the packages. With a total frequency multiplication factor of 36 and an active balun at the first stage, the transmitter allows the use of a 4.5-GHz input signal driven from a single-ended signal source [1] and distributed on a standard low-cost printed circuit board. The receiver comprises a Gilbert-cell-based subharmonic mixer with a simulated 1-dB input compression point of −4 dBm, and a minimum double-sideband noise figure of 16.5 dB. The functionality of the proposed system was successfully demonstrated in a quasi-monostatic FMCW radar measurement with a 1-ms up-chirp frequency sweep from 157 to 160 GHz and in a forward-scatter imaging experiment with an 8-GHz frequency ramp from 157 to 165 GHz.

Design and characterization of an integrated microwave generator for BIST applications

This paper presents a circuit architecture for a new integrated on chip test method for microwave circuits. The proposed built-in-self-test (BIST) cell targets a direct low-cost measurement technique of the gain and the 1 dB input compression point (CP1) of a K-band satellite receiver in the 18–22 GHz frequency bandwidth. A signal generator at the radiofrequency (RF) front end input of the device under test (DUT) has been integrated on the same chip. To inject this RF signal, a loopback technique has been used and the design has been accommodated for it. This paper focuses on the design of the most sensitive block of the BIST circuit, i.e. the RF signal generator. This circuit, fabricated in a SIGe:C BiCMOS process, consumes 10 mA. It presents a dynamic power range of 17 dB (−41; −24 dBm) and operates in a frequency range of 5.6 GHz (17.5; 23 GHz). This BIST circuit gives new perspectives in terms of test strategy, cost reduction, and measurement accuracy for microwave-integrated circuits and could be adapted for mm-wave circuits.

A 0.7–2.7-GHz Blocker-Tolerant Compact-Size Single-Antenna Receiver for Wideband Mobile Applications

Passive-mixer-first receivers have recently demonstrated flexible, low-noise, and high-linearity performance. Likewise, capacitive coupling element antennas have been demonstrated to be a viable choice for mobile handset integration. This paper combines these two advances into a single-antenna wideband receiver that achieves a 0.7-2.7-GHz reception band. The compact-size wideband tunable antenna achieves an efficiency of 45%-69% and occupies a volume of 2500 mm3. The front-end integrated circuit achieves an input compression point of +5 dBm with a noise figure of 4 dB while occupying only 0.3 mm2 of active die area. Additionally, an interface impedance study is performed to find the optimal impedances around the passive mixer and to demonstrate the different design tradeoffs of a passive-mixer-first receiver. A local oscillator duty-cycle adjustment circuit and its effect on the receiver performance is also presented.

A Low Power Inductorless LNA With Double ${\rm G} _{\rm m}$ Enhancement in 130 nm CMOS

This paper presents the design of a low power differential Low Noise Amplifier (LNA) in 130 nm CMOS technology for 2.45 GHz ISM band applications. The circuit benefits from several gm-enhancements. These techniques provide a high gain and reduced Noise Figure (NF) in spite of the low intrinsic gm of the MOS transistors. Moreover, the circuit is fully inductorless. Main design points are described and the performance tradeoffs of the circuit are discussed. A prototype has been implemented and it exhibits a 20 dB gain with a 4 dB NF while dissipating 1.32 mW. The IIP3 is -12 dBm for an input compression point of -21 dBm.

A Fundamental Frequency 120-GHz SiGe BiCMOS Distance Sensor With Integrated Antenna

This paper describes the first fundamental frequency single-chip transceiver operating at -band. The low-IF monostatic transceiver integrates on a single chip two 120-GHz voltage-controlled oscillators (VCOs), a 120-GHz divide-by-64 chain, two in-phase/quadrature (IQ) receivers with phase-calibration circuitry, a variable gain transmit amplifier, an antenna directional coupler, a patch antenna, bias circuitry, a transmit power detector, and a temperature sensor. A quartz antenna resonator with 6-dBi gain and simulated 50% efficiency is placed directly above the on-chip patch to transmit and receive the 120-GHz signals. The circuit with the above-integrated-circuit antenna occupies an area of 2.2 mm 2.6 mm, consumes 900 mW from 1.2- and 1.8-V supplies, and was wire-bonded in an open-lid 7 mm 7 mm quad-flat no-leads package. Some transceiver performance parameters were characterized on the packaged chip, mounted on an evaluation board, while others, such as receiver noise figure and VCO phase noise at the 120-GHz output were measured on circuit breakouts. The AMOS-varactor VCOs have a typical phase noise of at 1-MHz offset and a tuning range of 115.2-123.9 GHz. The receiver gain and the transmitter output power are each adjustable over a range of 15 dB with a maximum transmitter output power of 3.6 dBm. The receiver IQ phase difference, measured at the IF outputs of the packaged transceiver, is adjustable from 70° to 110°, while the amplitude imbalance remains less than 1 dB. The receiver breakout gain and double-sideband noise figure are 10.5-13 and 10.5-11.5 dB, respectively, with an input compression point of . Several experiments were conducted through the air over distances of up to 2.1 m with a focusing lens placed above the packaged chip.

A 160-GHz low-noise downconversion receiver front-end in a SiGe HBT technology

A 160-GHz SiGe-HBT (Heterojunction Bipolar Transistor) down-conversion receiver front-end for use in active millimeter-wave imaging arrays and D-band communication applications is presented. The monolithic front-end consists of a three-stage low-noise amplifier providing 24 dB of gain and a Gilbert-cell mixer capable of operating from a −8-dBm LO signal. A fully differential architecture compatible with balanced on or off-chip antennas is used to avoid the need for on-chip baluns in antenna-integrated applications. The implemented downconversion front-end consumes 50 mA from a 3.3 V supply and requires a 0.1 mm2 die area (excl. pads) per channel. With a 160-GHz input signal and an Intermediate Frequency (IF) of 1 GHz, the implemented front-end yields a 25-dB conversion gain, a −30-dBm input compression point, and a 9-dB/7-dB (with/without auxiliary on-chip input balun) system noise figure.

A Biphase Modulator Circuit for Impulse Radio-UWB Applications

This letter presents a circuit to provide binary phase shift keying to ultra-wideband (UWB) impulse transmitters. The circuit is based on a Gilbert-cell multiplier and uses active on-chip balun and unbalanced-to-balanced converters for single-ended to single-ended operation. Detailed measurements of the circuit show a gain ripple of ±1 dB at an overall gain of -2 dB, an input reflection below -12 dB, an output reflection below -18 dB, a group delay variation below 6 ps and a -1 dB input compression point of more than 1 dBm in both switching states over the full 3.1-10.6 GHz UWB frequency range. A time domain measurement verifies the switching operation using an FCC-compliant impulse generator. The circuit is fabricated in a 0.8 ?m Si/SiGe HBT technology, consumes 31.4 mA at a 3.2 V supply and has a size of 510 × 490 ?m2, including pads. It can be used in UWB systems using pulse correlation reception or spectral spreading.

A low local oscillator power K‐band mixer based on tunneling diodes

AbstractIn this article, we will demonstrate a low local oscillator (LO) power K‐band mixer based on a tunneling diode technology. Due to its unique diode characteristics, no DC supply is needed, whereas an LO power as low as −2 dBm is required for nominal functionality. The energy‐efficient MMIC prototype integrates a pair of heterojunction interband tunnel diodes and a 90° coplanar broadband coupler. The prototype is optimized within the 19–26 GHz band, with an IF ranging from zero to 7 GHz. In addition, when compared with other mixers, it has the lowest LO power requirement with a conversion loss ranging from 6 to 10 dB, an input compression point of −3 dBm and an intercept 2nd and 3rd order intermodulation point of 22 and 12 dBm, respectively. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 1140–1143, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24228

UHF RFID Reader With Reflected Power Canceller

Reflected power imposes severe linearity problems to the receiver in radio frequency identification (RFID) readers. In this letter, the design and realization of a ultra high frequency RFID reader with a reflected power canceller circuit based on quadrature feedback are presented. Theory and measurements of the signal and noise in the receiver are presented as a function of incident carrier power. The receiver sensitivity is even better than without the canceller with high incident carrier power: A noise spectral density at the data band is -140 dBm/Hz at +12 dBm incident carrier power. At the same time, input compression point of +15 dBm is achieved. The dynamic range of the receiver is improved by 10 dB.

Millimeter-Wave Integrated Circuits in 65-nm CMOS

We present the design and measurement results of millimeter-wave integrated circuits implemented in 65-nm baseline CMOS. Both active and passive test structures were measured. In addition, we present the design of an on-chip spiral balun and the transition from CPW to the balun and report transistor noise parameter measurement results at V-band. Finally, the design and measurement results of two amplifiers and a balanced resistive mixer are presented. The 40-GHz amplifier exhibits 14.3 dB of gain and the 1-dB output compression point is at +6-dBm power level using a 1.2 V supply with a compact chip area of 0.286 mm2. The 60-GHz amplifier achieves a measured noise figure of 5.6 dB at 60 GHz. The AM/AM and AM/PM results show a saturated output power of +7 dBm using a 1.2 V supply. In downconversion, the balanced resistive mixer achieves 12.5 dB of conversion loss and +5 dBm of 1-dB input compression point. In upconversion, the measured conversion loss was 13.5 dB with -19 dBm of 1-dB output compression point.

A 220 GHz (G-Band) Microstrip MMIC Single-Ended Resistive Mixer

This letter presents the design and characterization of a 220 GHz microstrip monolithic microwave integrated circuit single-ended resistive mixer in a 0.1 GaAs mHEMT technology. A conversion loss as low as 8.7 dB is obtained, limited by the available local oscillator (LO) power (1.5 dBm) in the measurement setup. The radio frequency (RF) bandwidth is also limited by the measurement setup, but the mixer demonstrates a flat response over the measured 200 to 220 GHz frequency range. Furthermore, measured intermediate frequency bandwidth, 1-dB input compression point, LO-to-RF isolation, and reflection coefficients are presented and discussed.

RF CMOS body-effect circuits

After a theoretical and analytical study of the body effect in MOS transistors, this paper offers two useful models of this parasitic phenomenon. Thanks to these models, a design methodology, which takes advantage of the bulk terminal, allows to turn this well-known body-effect drawback into an analog advantage, giving thus an efficient alternative to overcome the design constraints of the CMOS VLSI wireless mass market. To illustrate the approach, four RF building blocks are presented. First, a 0.9V 10dB gain LNA, covering a frequency range 1.8–2.4GHz, thanks to a body-effect common mode feedback, is detailed. Secondly, a body-effect linearity controlled pre-power amplifier is presented exhibiting a 5dBm input compression point (ICP1) variation under 1.8V power supply for half the current consumption. Lastly, two mixers based on body-effect mixing are presented, which achieve a 10dB conversion gain under 1.4V for a −52dB LO-to-RF isolation. Well suited for low-power/low-voltage applications, these circuits implemented in a 0.18μm CMOS VLSI technology are dedicated to multi-standard architectures and system-on-chip implementations.

8 GHz 1V, CMOS quadrature downconverter for wireless applications

The design and implementation of an 8 GHz CMOS quadrature downconverter, achieving simultaneously low voltage supply operation and good linearity is presented in this paper. This is achieved by relaxing the inherent tradeoff between power conversion gain and linearity governing all active mixers and implementing a mixer using a new version of the bias-offset technique. The quadrature generator uses active inductors embodied in the LO buffer, and provides easy tuning by relaxing the coupling between amplitude and phase tuning of the outputs. It also provides reduced power consumption by eliminating the buffers located between the quadrature generator and the mixers. A prototype implemented in a 0.18 ?m CMOS technology occupies an area of 0.44 × 0.3 mm2, operates from a 1V power supply and features an IIP3 of +3.5 dBm, an IIP2 of better than +48 dBm, an input compression point of ?5.5 dBm, a power conversion gain of +6.5 dB for the mixers and a quadrature phase and amplitude matching of better than 1.5° and 1 dB respectively over a bandwidth of 100 MHz after tuning. The overall power consumption of the quadrature downconverter is 25.8 mW.