An Integrated 65-nm CMOS SOI Ka-Band Asymmetrical Single-Pole Double-Throw Switch Based on Hybrid Couplers

Abstract

This letter presents the design of an asymmetrical Ka-band single-pole double-throw (SPDT) switch, based on two integrated hybrid couplers. The principle of operation of this switch and its two asymmetrical receiving (Rx) and transmitting (Tx) states are detailed. The circuit theory is supported by the implementation of a demonstrator using an advanced integrated technology: 65-nm substrate on insulator (SOI) CMOS from STMicroelectronics. To the author's best knowledge, it is the first implementation of such topology using an integrated CMOS technology. The demonstrator is designed considering a system-level tradeoff between the two states, in order to implement 28-GHz duplexers for 5G front-end modules (FEMs). The Rx state exhibits 1.9 dB of insertion loss, 24 dB of isolation and a 1 dB input compression point of 17.5 dBm, whereas the Tx state has 2.9 dB and 35 dB of insertion loss and isolation, respectively. Besides, the gain compression in the Tx state is lower than 0.3 dB, considering an input power of 18 dBm.