Input Bits Research Articles

A novel design of fast and compact all-optical full-adder using nonlinear resonant cavities

In this paper, we report a new design of an all-optical full-adder using two nonlinear resonators. The PhC-based full-adder consists of three input ports (A, B, and C for input bits), two nonlinear resonant cavities, several waveguides, and two output ports (for the SUM and CARRY). Eight silicon rods and a nonlinear rod composed of doped glass form each resonant cavity. The well-known plane wave expansion technique is used to calculate the photonic band structure. It shows a wide photonic bandgap in the wavelength range of 1365–2074 nm covering the C and L optical transmission bands. The finite-difference time-domain method is applied to study the light propagation inside the full-adder. Our numerical results demonstrate when the incoming light intensity increases, the nonlinear optical Kerr effect appears and controls the direction of light emitted inside the structure as desired. The maximum time delay and footprint of the proposed full-adder are about 3 ps and 758.5 μm2, respectively. Therefore, due to the low time delay and small footprint, the presented design can be used as a basic mathematical operator in the all-optical arithmetic logic unit.

High accurate multipliers using new set of approximate compressors

Approximate multipliers play vital role in the error-resilience applications by balancing accuracy and power efficiency. In this article, we improved the accuracy of approximate multipliers using a set of proposed approximate compressors which are able to compress any number of inputs to arbitrary numbers of output bits. To achieve better accuracy, probability of being one in the input bits is used to determine the compression ratio. Also, a novel scheme for allocating approximate and exact compressors in PPM is proposed to decrease column reduction stages. Error metrics namely PE, MED, MRED, and NED are calculated to evaluate accuracy of our approximate compressors. Experimental results show an average of 35% accuracy improvement, in comparison with the previous approximate compressors. We implemented four different multipliers including 8-bit, 12-bit, 16-bit, and 24-bit multipliers to prove goodness of our proposed algorithm. The multipliers are designed by Verilog and synthesized in a 45-nm standard CMOS technology. The experimental results demonstrate major accuracy superiority of our proposed multipliers in comparison with the state of the art approximate multipliers in terms of MED, MRED, and NED. According to the experimental results, the delay is improved 22%, on average, compared with exact multipliers.

Priority Based Switching of Loads Using PLC and SCADA

PLC is a medium between electrical systems and personal computers for SCADA to take input and output bits. SCADA and PLC communication systems make it possible to integrate protection control and monitor electrical parameters together for maximum benefit. The idea is to provide continuous power supply to the load, based on the priority by switching the loads. In case any one of the sources is absent i.e., source 1, source 2 and source 3, then automatically the least priority load cuts-off and first priority load gets supply continuously.

SAVINGS TIME EXECUTION PRIMA NUMBERS GENERATOR USING BIT-ARRAY STRUCTURE

Prime number in growth computer science of number theory and very need to yield an tool which can yield an hardware storey level effectiveness use efficiency and Existing Tools can be used to awaken regular prime number sequence pattern, structure bit-array represent containing subdividing variables method of data aggregate with every data element which have type of equal, and also can be used in moth-balls the yielded number sequence. Prime number very useful to be applied by as bases from algorithm kriptografi key public creation, hash table, best algorithm if applied hence is prime number in order to can minimize collision (collisions) will happen, in determining pattern sequence of prime number which size measure is very big is not an work easy to, so that become problems which must be searched by the way of quickest to yield sequence of prime number which size measure is very big Serial use of prosesor in seeking sequence prime number which size measure is very big less be efficient remember needing of computing time which long enough, so also plural use prosesor in seeking sequence of prime number will concerning to price problem and require software newly. So that by using generator of prime number use structure bit-array expected by difficulty in searching pattern sequence of prime number can be overcome though without using plural processor even if, as well as time complexity minimization can accessed. Execution time savings gained from the research seen from the research data, using the algorithm on the input Atkins 676,999,999. 4235747.00 execution takes seconds. While the algorithm by using an array of input bits 676,999,999. 13955.00 execution takes seconds. So that there is a difference of execution time for 4221792.00 seconds.

Probabilistic Shaping for Protograph LDPC-Coded Modulation by Residual Source Redundancy

Probabilistic amplitude shaping (PAS) has proved to be a promising way to achieve the shaping gain for an additive white Gaussian noise channel with a distribution matcher (DM). However, the DM schemes may suffer a rate loss and increase both complexity and latency, when they are not suited for the input bit stream with redundancy. In this paper, a novel PAS strategy is proposed for a joint source and channel coded modulation system, where the residual source redundancy after source coding can be exploited to obtain both shaping and coding gains. It is shown that the residual source redundancy can be controlled by choosing the row weight distribution for source code, thus making the probability distribution of the modulated symbols be optimized under an appropriate interleaver design. To guarantee the error-floor performance, the source code is constrained by predicting the probability distribution of source bits within target finite-length frames. By jointly designing source and channel codes, the residual source redundancy can also be exploited to achieve the coding gain. Compared with the state-of-the-art code pairs, the proposed code pairs have better error-floor performance, and achieve higher coding and shaping gains without suffering from the rate-loss and the latency caused by DM.

Efficient Designs of Reversible Shift Register Circuits with Low Quantum Cost

Reversible computations have attracted a lot of attention in recent years due to the ability to reduce energy dissipation that is needed in nanocircuits. The main purpose of designing reversible circuits is to reduce the energy consumption that occurs due to the loss of input bits in irreversible circuits. In this paper, we initially proposed a new [Formula: see text] reversible block and then its quantum realization is given using the Miller et al. method. In the following, an effective reversible design of D flip-flop is introduced using the proposed reversible block. Finally, four types of reversible shift register including serial-in to parallel-out (SIPO), parallel-in to parallel-out (PIPO), parallel-in to serial-out (PISO) and shift counter are proposed using the proposed reversible flip-flop. The evaluation results show that the proposed circuits are superior compared to the existing designs in terms of quantum cost (QC).

Blind reconstruction of punctured convolutional codes

Blind reconstruction of punctured convolutional codes is an important problem in non-cooperative communications. In this problem, the goal is to identify the employed mother code and the puncturing pattern. The state-of-the-art method employs a two-stage algebraic-based search technique. First, all the equivalent non-punctured encoders are reconstructed. Then, the mother code and the puncturing pattern are identified by searching over all equivalent encoders. In some cases, the number of equivalent encoders is very large that makes the reconstruction process very complex, time-consuming, and impractical. In this paper, we propose an algebraic-based search method for reconstruction of the mother code and the puncturing pattern that significantly reduces the complexity of blind reconstruction. The problem is formulated and solved in the general case of mother codes with more than one input bit. The proposed algorithm also works well for non-punctured convolutional codes.

Dimming controlled multi header hybrid PPM (MH-HPPM) for visible light communication

Visible Light Communication (VLC), which gives communication alongside illumination, has increased a great deal of enthusiasm amongst researchers. VLC system needs to consider dimming control to offer effective communication while illuminating. In this paper, a dimming control scheme based on pulse position modulaton (PPM) and inverse PPM is proposed, which supports different dimming levels. PPM supports low dimming value whereas inverse-PPM has an inherent property of supporting higher dimming value for the same block length. Hence, the proposed scheme utilizes both PPM and inverse-PPM to achieve different dimming target values. This paper presents the algorithm for encoding and decoding of multi-header hybrid pulse position modulation (MH-HPPM) scheme and also shows the NI Labview SubVI code for generating the MH-HPPM frame under dimming values of 0.25, 0.33, 0.5, 0.67 and 0.75. Simulations are executed in MATLAB 2017a to simulate random input bits using the proposed scheme in the VLC system for different dimming values and evaluate the BER performance of the scheme. The simulation result shows that the proposed scheme performs better for dimming value $$\alpha = 0.25$$ , block length $$K = 4$$ , is bandwidth efficient and hence can be considered as an alternate dimming control scheme.

Designing Substitution Box Based on the 1D Logistic Map Chaotic System

Many researchers have tried to use the chaotic systems in generating different cryptographic tools, in order to provide high level of security to the data passing through network. In modern symmetric cryptographic systems, one of the most essential functions is a nonlinear mapping Substitution process which is responsible for creating the confusion between plaintext and ciphertext. It replaces each input bits by other bits using the lookup table S-Box. In this paper a new S-Box based on a 1D logistic map chaotic system was designed. The chaotic sequence generated from the 1D logistic map was processed to generate the hexa code values, and after that this hexa code also processed to construct the new good S-Box. This proposal was evaluated using the S-Box tests criteria including avalanche, balanced, completeness, strict avalanche, and invertibility. The analysis results show that the proposed S-Box passes all these statistical tests, has large avalanche effect and therefore the S-Box can avoid many attacks. The construction of both Substitution-Box and its inverse take only few milliseconds, so it can be used in many lightweight block ciphers.

Device-independent randomness expansion with entangled photons

With the growing availability of experimental loophole-free Bell tests1–5, it has become possible to implement a new class of device-independent random number generators whose output can be certified6,7 to be uniformly random without requiring a detailed model of the quantum devices used8–10. However, all these experiments require many input bits to certify a small number of output bits, and it is an outstanding challenge to develop a system that generates more randomness than is consumed. Here we devise a device-independent spot-checking protocol that consumes only uniform bits without requiring any additional bits with a specific bias. Implemented with a photonic loophole-free Bell test, we can produce 24% more certified output bits (1,181,264,237) than consumed input bits (953,301,640). The experiment ran for 91.0 h, creating randomness at an average rate of 3,606 bits s–1 with a soundness error bounded by 5.7 × 10−7 in the presence of classical side information. Our system allows for greater trust in public sources of randomness, such as randomness beacons11, and may one day enable high-quality private sources of randomness as the device footprint shrinks. Device-independent randomness expansion is demonstrated in an experiment that is secure in the presence of a classical eavesdropper who does not share any entanglement with the setup.

On Hardware Implementation of Balanced S-boxes

An S-box is a non-linear transformation that takes n bits as input and returns m bits. This transformation is most easily represented as a nm lookup table. Most often, only balanced S-boxes are used in cryptography. This means that the number of input bits is equal to the number of output bits. The S-box is an important part of most symmetric ciphers. The selection of the correct substitution makes the link between the key and the ciphertext more complex (non-linear), which makes it much more difficult to hack. This paper deals with a hardware implementation of S-boxes. This implementation can be realized by using logical conjunction, disjunction, negation and delay blocks. The main indicator of productivity of such implementations is a circuit depth, namely the maximum length of a simple way of the circuit and a circuit complexity, namely the quantity of logic elements (negation elements are not taken into account). The article considers the standard synthesis methods (based on DNF, Shannon, Lupanov), proposes a new algorithm to minimize the complexity of an arbitrary Boolean functions system and a way to reduce the complexity of the circuit obtained after simplification by the ESPRESSO algorithm of DNF of the function related to the output of the S-box. To compare the efficiency of the methods, the C++ program was created that generates a circuit in the Verilog language. The estimates of depth and complexity are obtained for the schemes produced as a result of the programs operation. The article ends with a comparison of the efficiency of S-box schemes of known cryptographic standards obtained as the output of the program (with each other and with the result of the Logic Friday program).

Performance Enhancement of Gaussian Minimum Shift Keying Using Optimum Phase Sampling Technique for Turbulent Free-Space Optical Communication

In this paper, analytical performances of Gaussian minimum shift keying (GMSK) are studied for free space optical communication system. Authors propose an innovative sampling technique called, optimum phase sampling technique to investigate the bit error performance of GMSK modulation. Subsequently, performances of GMSK like, bit error rate (BER), power spectral density, and adjacent carrier interference (ACI) have also been investigated and compared with other modulation techniques. Furthermore, return to zero (RZ) coding input bit stream prior to GMSK technique improves the ACI performance of GMSK. To end with, we present the improvement of degradation parameter (γ) in a tabular form through phase sampling technique. Moreover, both optimum phase sampling and narrow pulse shaping of RZ-GMSK obtains near optimal result of BER. The numerical results show, that the proposed phase sampled RZ-GMSK of 70% duty cycle at BT = 0.6 has a degradation value of 0.979, which is comparable to GMSK at BT = ∞. Moreover, the proposed RZ-GMSK achieves lower ACI value and has an error rate of 7 × 10−7, which is lower than the GMSK of 1 × 10−6 BER value.

WITHDRAWN: Hybrid neural synchronization blowfish algorithm for secret key exchange over public channels

A secured Exchange of information between authorized or dedicated users over the public channels without revealing information to anyone of unauthorized users is the main purpose of a cryptographic system. Since a large computation power is required in cryptographic systems and is involves with complex process, commonly shared secret keys are generated by using the neural synchronization based algorithms which in turn use a large number of learning rules for the exchanging of these secret keys on public channels. In this paper, the secret key is formed as input bits of a neural network on a public channel using a hybrid Blowfish (BF) algorithm for the securing of the files. The information files or messages sent through a public channel can be encrypted and decrypted by using this generated secret key. In this, first he two communication networks in this neural cryptography system produce mutual output bits by receiving the identical input vectors and are trained on their mutual output bits. Identical time independent vectors are calculated to synchronize these communication networks upto a state. Then the generated common secret key can be exchanged on public channels. This secret key can be utilized for the implementation of any encryption and decryption algorithms. According to the throughput and runtimes the proposed algorithm is analyzed by using the medical report files.

Generalized SAT-Attack-Resistant Logic Locking

Logic locking is used to protect integrated circuits (ICs) from piracy and counterfeiting. An encrypted IC implements the correct function only when the right key is input. Many existing logic-locking methods are subject to the powerful satisfiability (SAT)-based attack. Recently, an Anti-SAT scheme has been developed. By adopting two complementary logic blocks that consist of AND/NAND trees, it makes the number of iterations needed by the SAT attack exponential to the number of input bits. Nevertheless, the Anti-SAT scheme is vulnerable to the later AppSAT and removal attacks. This paper proposes a generalized (G-)Anti-SAT scheme. Different from the Anti-SAT scheme, a variety of complementary or non-complementary functions can be adopted for the two blocks in our G-Anti-SAT scheme. The Anti-SAT scheme is just a special case of our proposed design. Our design can achieve higher output corruptibility, which is also tunable, so that better resistance to the AppSAT and removal attacks is achieved. Meanwhile, unlike existing AppSAT-resilient designs, our design does not sacrifice the resistance to the SAT attack.

High Quality Down-Sampling for Deterministic Approaches to Stochastic Computing

Deterministic approaches to stochastic computing (SC) have been recently proposed to remove the random fluctuation and correlation problems of SC and so produce completely accurate results with stochastic logic. For many applications of SC, such as image processing and neural networks, completely accurate computation is not required for all input data. Decision-making on some input data can be done in a much shorter time using only a good approximation of the input values. While the deterministic approaches to SC are appealing by generating completely accurate results, the cost of precise results makes them energy inefficient for the cases when slight inaccuracy is acceptable. In this work, we propose a high quality down-sampling method for previously proposed deterministic approaches to SC by generating pseudo-random-but accurate-stochastic bit-stream. The result is a much better accuracy for a given number of input bits. Experimental results show that the processing time and the energy consumption of these deterministic methods are improved up to 61 and 41 percent, respectively, while allowing a mean absolute error (MAE) of 0.1 percent, and up to 500X and 334X improvement, respectively, for an MAE of 3.0 percent. The accuracy and the energy consumption are also improved compared to conventional random stream-based stochastic implementations.

A Novel Multiplier-Less LMS Adaptive Filter Design Based on Offset Binary Coded Distributed Arithmetic

Multiply-Accumulate (MAC) operation is the backbone of Least Mean Squares (LMS) digital adaptive filters. Implementing LMS on hardware platform as a Fully Dedicated Architecture (FDA) multiplier becomes bottleneck for higher order filters, prompting high area, cost and power requirements and hence renders the design unsuited for practical implementation. In this paper, we have proposed a composite design that makes use of Distributed Arithmetic (DA) to replace the bottleneck multiplier with memory units that store Partial Products (PPs) to emulate multiplication. The depth of these memory units tends to exponentially grow as the filter order rises. To manage that, we have used Half Memory algorithm (HM) and Offset Binary Coding (OBC) to refine the structure of PPs such that the memory size is reduced at least by a factor of 4 for the same filter order. The proposed design improves system's Throughput, Critical Path Delay, Power Consumption and FPGA Resource Utilization. However, it introduces Latency in both the output and update segments of the LMS algorithm. To provide an option between resource utilization and latency, we have suggested a mechanism to halve the originally produced latency by the Parallel Processing of input bit steam w.r.t even and odd bits. Moreover, we have also proposed a method that reduces the latency of update module at the slight expense of other design attributes. The fundamental structure of the proposed design is flexible owing to the dynamic memory structure as well as the option to choose between latency and resource minimization. Simulations have been carried out in Xilinx Vivado and conclusions have been drawn by comparing both FDA and DA based designs. Results for a 16-tap filter indicate a remarkable improvement in Throughput, Area Utilization and Power Consumption by 18%, 5% and 3.5% respectively at the expense of 4× escalated latency. The Half Latency method allowed the latency to drop 2× but with slightly elevated power and area attributes.

SUPERVEGAN: Super Resolution Video Enhancement GAN for Perceptually Improving Low Bitrate Streams

This paper presents a novel model family that we call SUPERVEGAN, for the problem of video enhancement for low bitrate streams by simultaneous video super resolution and removal of compression artifacts from low bitrates (e.g. 250Kbps). Our strategy is fully end-to-end, but we upsample and tackle the problem in two main stages. The first stage deals with removal of streaming compression artifacts and performs a partial upsampling, and the second stage performs the final upsampling and adds detail generatively. We also use a novel progressive training strategy for video together with the use of perceptual metrics. Our experiments shown resilience to training bitrate and we show how to derive real-time models. We also introduce a novel bitrate equivalency test that enables the assessment of how much a model improves streams with respect to bitrate. We demonstrate efficacy on two publicly available HD datasets, LIVE-NFLX-II and Tears of Steel (TOS). We compare against a range of baselines and encoders and our results demonstrate our models achieve a perceptual equivalence which is up to two times over the input bitrate. In particular our 4X upsampling outperforms baseline methods on the LPIPS perceptual metric, and our 2X upsampling model also outperforms baselines on traditional metrics such as PSNR.

Rate Adaptability Using LUT-Based Distribution Matching for Probabilistic Constellation Shaping

We investigate the flexibility of a LUT-based hierarchical DM for Probabilistic Constellation Shaping providing flexible net bit rates. Using a fixed parallelized input and output LUT-based architecture, including a flexible strategy to organize the input bits in each LUT, the proposed scheme shows an efficient performance in terms of rate loss vs. complexity, resulting in a DM solution to enable flexible bit rates with improved channel transmission. We use an 800G example design with soft-decision FEC to discuss the optimization strategy and to demonstrate the flexibility of the proposed method, enabling a high granularity bit rate operation in the range of 160 to 800Gb/s with a rate loss always below 0.14bits/symbol.

Design and Implementation of a Lossless Compression System for Hyperspectral Images

Despite its popularity, the hyperspectral image compression algorithm recommended by the Consultative Committee for Space Data Systems (CCSDS) faces a long delay of the feedback loop and complex computations in the modes of band sequential (BSQ) and band interleaved by line (BIL). After analyzing the features of the CCSDS algorithm, this paper proposes a forward prediction method based on the xc7k325tffg9000 field programmable gate array (FPGA) chip (Xilinx Inc.), and adjusts the calculation flow of the CCSDS algorithm, aiming to shorten the time delay in the feedback loop. In addition, full-pipeline construction was implemented on FPGA board to realize real-time processing of data, and dynamic configuration of image parameters. Through functional simulation and off-board test, it is learned that, for the speed-insensitive path, the optimized algorithm can realize the complex operations of the original algorithm with less hardware resources; for hyperspectral image data with an effective input bit width of 12bit, the proposed method can reach a maximum operating frequency of 103MHz, and the data throughput of 103M samples per second (1.237Gbps).

Lipschitz bijections between boolean functions

AbstractWe answer four questions from a recent paper of Rao and Shinkar [17] on Lipschitz bijections between functions from {0, 1}n to {0, 1}. (1) We show that there is no O(1)-bi-Lipschitz bijection from Dictator to XOR such that each output bit depends on O(1) input bits. (2) We give a construction for a mapping from XOR to Majority which has average stretch $O(\sqrt{n})$ , matching a previously known lower bound. (3) We give a 3-Lipschitz embedding $\phi \colon \{0,1\}^n \to \{0,1\}^{2n+1}$ such that $${\rm{XOR }}(x) = {\rm{ Majority }}(\phi (x))$$ for all $x \in \{0,1\}^n$ . (4) We show that with high probability there is an O(1)-bi-Lipschitz mapping from Dictator to a uniformly random balanced function.