InP Heterojunction Bipolar Transistors Research Articles

An Aging Small-Signal Model for Degradation Prediction of Microwave Heterojunction Bipolar Transistor S-Parameters Based on Prior Knowledge Neural Network.

In this paper, an aging small-signal model for degradation prediction of microwave heterojunction bipolar transistor (HBT) S-parameters based on prior knowledge neural networks (PKNNs) is explored. A dual-extreme learning machine (D-ELM) structure with an adaptive genetic algorithm (AGA) optimization process is used to simulate the fresh S-parameters of InP HBT devices and the degradation of S-parameters after accelerated aging, respectively. In addition to the reliability parametric inputs of the original aging problem, the S-parameter degradation trend obtained from the aging small-signal equivalent circuit is used as additional information to inject into the D-ELM structure. Good agreement was achieved between measured and predicted results of the degradation of S-parameters within a frequency range of 0.1 to 40 GHz.

Small-signal behavioral-level modeling of InP HBT based on SO-BP neural network

In this paper, Snake Optimizer-Back Propagation (SO-BP) neural network algorithm has been proposed to model the small-signal characteristic of InP heterojunction bipolar transistors (HBTs). The SO algorithm can effectively improve the problem of local optima encountered by the BP neural network algorithm. The InP HBT small-signal models have been constructed by using Back Propagation (BP) algorithm, the Genetic Algorithm-Back Propagation (GA-BP) algorithm and the Snake Optimizer-Back Propagation (SO-BP) algorithm. The experimental results verify that the proposed SO-BP neural network algorithm model has the lowest error rate between simulated and measured data. Hence, the SO-BP algorithm is a more effective approach for modeling the small-signal characteristic of InP HBT. The accurate small-signal behavioral-level model of HBT has significant reference value for the application of microwave and millimeter-wave integrated circuits (MMICs).

(Invited) Integration of InP Heterojunction Bipolar Transistors on Silicon Substrates for 6G Networks

The fast expansion of the global datasphere creates a huge demand on the future wireless communication technologies. Although 5G, the 5th generation of the cellular network technology, is still being rolled out, the potential of 6G is already intensively explored. The vision of 6G implies not only massive connectivity and higher data rate (up to 100 Gb/s and more) in ultra-reliable low-latency communication, but machine-to-machine interaction will dominate over those involving humans. AI (artificial intelligence) and machine learning will be omnipresent.6G network will address a frequency spectrum beyond 100 GHz, which provides wider bandwidths and, therefore, potentially simpler modulation schemes and eventually lower power consumption. However, a clear disadvantage of these mm-waves or sub-THz frequencies are the atmospheric absorption and blockage effect by physical obstacles or rain. These challenges must be tackled by a sufficiently high transceiver device density per area together with advanced beam steering and AI empowered networks.The power amplifier (PA) is one of the most critical components of the RF front-end module. Here, InP based heterojunction bipolar transistors (HBT) clearly outperform PAs based on CMOS or SiGe BiCMOS concerning saturated output power, energy efficiency and breakdown voltage. However, the limiting downside of InP HBTs is the missing cost-efficient and scalable fabrication, which hampers its adoption in high-volume 6G applications. In this paper we review various InP HBT fabrication concepts with the aim of lowering the production costs and maintaining high device performance.The best HBT device performance is demonstrated for the lattice-matched deposition on native small-diameter (≤ 150 mm) InP substrates due to perfect III-V crystal quality. Although device fabrication on these wafers cannot profit from the advanced tool park available in 200/300 mm fabs, the main drawbacks are the high cost and brittleness of InP substrates. Realizing InP HBTs on Si substrates allows to benefit from their robustness, low cost, and the access to a mature device fabrication on large-diameter wafers.In wafer reconstitution, numerous diced InP wafer tiles, which already contain the grown HBT layer stack, are bonded to a Si carrier to populate the wafer surface. After planarization, the reconstructed Si wafer can be further fabricated in a CMOS compatible 200/300 mm fab. In transfer printing a comparable approach is followed while only the active device stack is transferred to the Si carrier. Transferring only a thin InP layer to the Si carrier, which serves as a starting surface for the HBT deposition, leads to a so-called engineered substrate. Compared to the previous transfer methods, the III-V device deposition is carried out after bonding. The key advantage of all these heterogenous integration concepts is the access to a CMOS compatible and scalable device fabrication while maintaining the high III-V crystal quality. Nevertheless, the HBT production costs can only be significantly reduced with a certain re-usability of the InP substrates.The monolithic deposition directly on Si substrates would be the most cost-efficient integration approach. Unfortunately, the mismatch in lattice constant and thermal expansion coefficient between Si and III-V materials leads to the formation of relaxation defects, which degrade the HBT device performance. The growth of thick strain relaxation buffers allows to reduce the defect density in the device layers but bears new challenges such as wafer warpage or III-V crack formation.Nano-ridge engineering (NRE) is based on selective area growth (SAG) applying trench-patterned Si wafers. The III-V deposition starts inside very narrow trenches to achieve efficient aspect ratio trapping (ART) of misfit defects. After the trench is filled with III-V material, the growth is continued to engineer a broad and pristine nano-ridge (NR) which holds the device stack. A second oxide pattern prevents sidewall deposition around the NRs during the deposition of the HBT heterolayers.In the first part of this paper, pros, and cons of the most common InP HBT integration scenarios as summarized in figure will be compared in detail. Among all concepts, NRE holds the potential of being the most cost-efficient integration approach due to SAG in line with very limited III-V material deposition. However, the key open question is what NR crystal quality, and hence, device performance can be realized. This question will be addressed in the second part of the paper, reporting about the latest developments at imec. Figure 1

A novel radiation-dependence model of InP HBTs including gamma radiation effects

In order to predict the lifetime of InP Heterojunction Bipolar Transistor (HBT) devices and related circuits in the space radiation environment, a novel model including gamma radiation effects is proposed in this paper. Based on the analysis of radiation-induced device degradation effects including both DC and AC characteristics, a set of empirical expressions describing the device degradation trend are presented and incorporated into the Keysight model. To validate the effective of the proposed model, a series of radiation experiments are performed. The correctness of the novel model is validated by comparing experimental and simulated results before and after radiation.

(Invited) Integration of InP Heterojunction Bipolar Transistors on Silicon Substrates for 6G Networks

The power amplifier (PA) in an RF front-end module operating above 100 GHz required for 6G wireless networks is the most power-hungry device circuit component. In that respect, InP-based heterojunction bipolar transistors (HBT) clearly outperform other PA technologies, but being processed on small size wafers, they lack a cost-effective fabrication for mass production. This paper presents a comprehensive comparison of various integration approaches for InP-based HBTs. A key aspect in achieving high yield device fabrication is the use of large-diameter silicon wafers. This study discusses the advantages and disadvantages of different InP-based HBT integration concepts on Si, emphasizing important factors for upscaling InP technologies. Furthermore, this work introduces nano-ridge engineering (NRE), a novel monolithic III-V integration approach currently being explored at imec, which holds the potential for cost-effective and complementary metal oxide semiconductor (CMOS)-compatible production.

Stacked Common-Base vs Common-Emitter mmWave PA Cells and 68–105 GHz Broadband Asymmetrical PA in 250nm InP HBT

In this paper, we perform a comparative analysis between stacked common-emitter (SCE) and stacked common-base topologies (SCB) for high efficiency and broadband millimeter-Wave (mmWave) power amplifiers (PAs) in 250 nm InP-based heterojunction bipolar transistor (HBT) technology. We propose an analytical approach to design stacked PA cells accounting for complex load impedance and intra-matching between stacked transistors to allow optimal loadpull operation of both the devices in the stack. We demonstrate how SCB cell can allow higher gain, mitigated power and efficiency trade-off and linearity, when compared to more well-established SCE cells at higher mmWave frequencies. The designed SCB and SCE cells achieve a measured gain of 11.8 dB/6dB gain, 33%/34% peak PAE, 16.8%/14.5% PAE at 6-dB back-off, and Psat of 18.7 dBm/19.6 dBm at 90 GHz. The SCB PA demonstrates superior linearity, and achieves an EVM of 2.38% at 11.8-dBm average power supporting 3 Gbps 64-QAM. The SCB PA achieves 17.9-18.9-dBm Psat across 80–110 GHz and is one of the highest efficiency, broadband and linear PAs in W-band using InP technology. Utilizing the PA cells, we demonstrate an asymmetrical broadband power combining circuit for high efficiency combining across a large relatively bandwidth. The PA operates across a 68–105 GHz <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{sat,3dB}$ </tex-math></inline-formula> bandwidth with 21.5 dBm peak saturation power and 24% peak PAE.

Small-signal Modeling of InP HBT based on PSO-ELM Neural Network

Extreme Learning Machine (ELM) is a new learning algorithm for single-hidden layer feedforward neural network, which has been widely used in lots of fields. However, it still has the insufficiency of randomly determining the hidden layer threshold and output weight, which leads to ill-conditioned output. In order to avoid the risk of decreasing prediction accuracy caused by this possibility, the ELM is optimized using particle swarm algorithm. A Particle Swarm Optimization (PSO) enhanced ELM algorithm is proposed to accurately model the small-signal properties of InP Heterojunction Bipolar Transistors (HBTs). PSOELM algorithm solves the problem of unstable prediction data caused by random determination of input weights in ELM. Comparing the modeling effects of the PSO-ELM model and the ELM model under different bias conditions for a 1 μm×15 μm InP HBT, it is proved that the PSO-ELM algorithm has better consistency with the measured data.

600-GHz High-Power Signal Sources Based on 250-nm InP HBT Technology

Two 600-GHz radiation signal sources, a single- and four-element oscillators, have been developed based on a 250-nm InP heterojunction bipolar transistor technology. The single-element unit oscillator adopts the common-emitter cross-coupled structure with reactive emitter degeneration, which enables second harmonic oscillation around 600 GHz with enhanced output power. Based on the unit oscillator, the four-element coupled oscillator with cascaded two-way shunt power combiners was developed to further increase the output power. Both oscillators are integrated with on-chip patch antennas with simulated antenna gain of 3.5 dBi and directivity of 8.0 dBi at 600 GHz. The measured oscillation frequencies of the two signal sources are 580–586 GHz and 583–591 GHz, respectively, varied with the base bias. They exhibited the measured peak effective isotropic radiation power (EIRP) of 1.1 and 2.7 dBm, respectively, which correspond to the radiated output power of −7.5 and −5.9 dBm. The total dc power consumptions are 34.5 and 129.6 mW, which lead to the estimated dc-to-RF efficiencies of 0.52 and 0.2% for the two sources. The measured phase noises are −88.6 and −90.1 dBc/Hz at 10-MHz offset frequency for the single- and four-element oscillators, respectively.

Real-Time Millimeter-Wave Imaging for Moving Targets Realized in a Sparse Array Based on InP-HBT MMICs

Millimeter-wave (MMW) imaging has been widely studied for applications, such as personnel screening and industrial noninvasive testing; however, real-time MMW imaging with a subcentimeter resolution and a large field of view (FoV) for a fast-moving target has been rarely reported to date. In this article, we present the design of such an imaging system at the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Ka$ </tex-math></inline-formula> -band utilizing the concept of multistatic sparse array. Microwave monolithic integrated circuits based on an InP-heterojunction bipolar transistor (HBT) technology are used for the transmitter and receiver chipsets. With the help of an improved backprojection algorithm and a computation platform based on field-programmable gate arrays, real-time imaging for a target moving as fast as about 10 m/s is demonstrated at a frame rate of over 20 frames/s. The imaging resolution is measured to be better than 6 mm and the FoV can reach over <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1\times 1\,\,\text{m}^{2}$ </tex-math></inline-formula> . Imaging of a moving person with concealed items is carried out to illustrate the system’s capability for personnel screening. To the best of the authors’ knowledge, this is the first real-time MMW sparse array imaging system built upon InP-HBT chipsets.

Parasitic parameters extraction of InP HBT only from S-parameters measured under cut-off and normal bias conditions

An improved parasitic parameters extraction method for InP heterojunction bipolar transistor (HBT) is developed. The difference between this method and previous methods is that all parasitic parameters can be extracted by relying only on the S-parameters measured under the cut-off and normal bias conditions. All the capacitance parameters in the equivalent circuit at the low-frequency cut-off can be extracted by combining the analytical closed formulas and the parameter scanning method. The intrinsic resistance Rbi is obtained indirectly by extracting the extrinsic resistance Re based on the Z-parameter method in the normal bias conditions. By de-embedding the parasitic capacitances, all the values of parasitic inductances and extrinsic resistances are obtained by the direct extraction method under the cut-off condition. The proposed method not only eliminates the critical measurement of the open-collector condition, but also greatly improves the efficiency and accuracy of parameter optimization. For different sizes and bias conditions of InP HBT devices, the excellent agreement between simulated and measured results is verified all over the frequency range of 0.4–50 GHz.

A Compact Macromodeling Method for Characterizing Large-signal DC and AC Performance of InP and GaAs HBTs

In this paper, a compact macromodeling method for characterizing the large-signal characteristics of heterojunction bipolar transistors (HBTs) is proposed and successfully applied to describe the DC and AC performance of InP and GaAs HBT devices. Using the Symbolically-defined Device (SDD) technology, an empirical macro circuit preserving the Spice Gummel-Poon (SGP) intrinsic network and a simplified thermal network is established. The empirical current and charge functions are embedded in the SDD macro circuit network module. Compared with other large-signal models, the proposed model description and the relevant parameter extraction are relatively simpler, and at the same time, this method can maintain high fitting accuracy. To assess the validity and the accuracy of the proposed model, the compact large-signal model is constructed for 1 ㎛ InP HBT and 1 ㎛ GaAs HBT. Based on the complete extraction of the model parameters, excellent consistency is obtained between the measured and modeled results.

An augmented small-signal model of InP HBT with its analytical-based parameter extraction technique

A rigorous and systematic analytical-based parameter extraction technique for the augmented small-signal equivalent-circuit model dedicated to III-V-based heterojunction bipolar transistors (HBTs) is presented. The proposed extraction method relies exclusively on S-parameters measured at low and high frequencies. The extraction algorithm is derived by peeling peripheral elements from the small-signal equivalent circuit with very few simplified approximations throughout the whole extraction process. All of the elements’ parameters of the small-signal equivalent-circuit model considering the base-collector and base-emitter capacitances distributed effect are determined accurately through the developed extraction technique. Excellent agreement is obtained demonstrating the comparisons between the small-signal S-parameters measured and modeled results for 0.7 μm InGaAs/InP HBTs over a wide range of bias points within the frequency range of 0.1–40 GHz, which verifies the validity and the accuracy of this model and extraction technique.

Terahertz Signal Source and Receiver Operating Near 600 GHz and Their 3-D Imaging Application

In this article, a set of oscillators and a heterodyne image receiver operating near 600 GHz have been developed, each based on a 250-nm InP heterojunction bipolar transistor (HBT) technology and a 130-nm SiGe HBT technology, respectively. The oscillators are based on the common-base cross-coupled push–push topology, which employed coupled-line loads for improved output power and efficiency with a small area. The measured oscillation frequency ranges of the three oscillators with different coupled-line lengths were 628–682, 556–610, and 509–548 GHz, respectively, with a tuning capability achieved with bias variation. The maximum output power and the dc-to-RF efficiency achieved with the oscillators were −10 dBm and 0.19%, respectively. The heterodyne receiver, which consists of a mixer, an IF amplifier, and an IF detector, exhibited a maximum responsivity of 469 kV/W and a minimum noise equivalent power (NEP) of 0.64 pW/Hz1/2. A transmission-mode 3-D THz tomography imaging setup was established with one of the fabricated oscillators and the heterodyne receiver employed as the signal source and the image detector, respectively. With the imaging setup, a successful reconstruction of 3-D images of a target object was demonstrated based on the filtered back-projection algorithm.

An improved small signal model of InP HBT for millimeter‐wave applications

AbstractIn this letter, an improved small‐signal equivalent circuit model of InP heterojunction bipolar transistors (HBTs) for millimeter‐wave applications is presented. The proposed small‐signal model takes into account the parasitic effect in the collector part which can effectively improve the accuracy of S parameter. In the frequency range of 2–110 GHz, good agreements between the measured and model‐calculated data can be achieved to demonstrate good modeling accuracy.

An Improved Nonlinear Model for Millimeter-Wave InP HBT Including DC/AC Dispersion Effects

An improved millimeter-wave nonlinear model for InP heterojunction bipolar transistor (HBT) is proposed in this letter. The frequency dispersion effect has been taken into account in the Agilent HBT model in Agilent ADS software. Model verification is carried out by comparison of measured and simulated dc and S-parameters up to 110 GHz.

80–110-GHz Broadband Linear PA With 33% Peak PAE and Comparison of Stacked Common Base and Common Emitter PA in InP

This work presents a high efficiency, compact 80-110-GHz InP power amplifier (PA) based on stacked common base (CB) topology and a counterpart design using conventional stacked common emitter (CE) topology. The comparison between the two exhibits that the former delivers higher power gain, superior-gain compression behavior (linearity), and higher back-off efficiency in W-band in 250-nm InP heterojunction bipolar transistor (HBT). At 90 GHz, the stacked CB/CE PA achieves 11.8 dB/6dB gain, 33%/34% peak PAE, 16.8%/14.5% PAE at 6-dB back-off, and Psat of 18.7 dBm/19.6 dBm. Modulation test exhibits an EVM of 2.38% at 11.8-dBm average power supporting 3 Gbps 64-QAM for the stacked CB PA. The stacked CB PA with 17.9-18.9-dBm Psat across 80-110 GHz demonstrates one of the highest efficiency, broadband and linear PAs in W-band using InP technology.

H-Band InP HBT Frequency Tripler Using the Triple-Push Technique

A broadband H-band (220 GHz–325 GHz) frequency tripler using the triple-push technique is presented in 250-nm InP heterojunction bipolar transistors (HBT) technology. It consisted of three identical unit-cell multipliers, which were individually pumped by the W-band input signals with 120° phase difference. For this purpose, a 120° 3-way power divider was proposed using the 1:2 and 1:1 Lange couplers with 30° phase delay lines. The fundamental and 2nd harmonic signals of each unit-cell multiplier were added out-of-phase at the output, allowing an effective harmonic suppression. On the contrast, the 3rd harmonic components were combined in-phase at the output, so that the entire circuit successfully did the function of the frequency multiplier-by-3. The fabricated frequency tripler exhibited a broadband output power of −7.4 ± 1.4 dBm from 225 GHz to 330 GHz at an input power of 9.6 ± 0.8 dBm, with an average conversion gain of −16.8 dB.

300-GHz InP HBT Quadrature VCO With Integrated Mixer

A 300-GHz quadrature voltage-controlled oscillator (QVCO) integrated with a pair of mixers based on an InP heterojunction bipolar transistor (HBT) technology has been developed. A super-harmonic coupling technique was applied to generate the quadrature signal in the QVCO. The oscillation frequency tuning range is 24.8 GHz (from 286.1 to 310.9 GHz), and the frequency range maintaining the quadrature operation (within ±10°) is 4.8 GHz (297.2–302.0 GHz). The maximum output power of the QVCO was measured as 0.46 dBm at 286.3 GHz. The measured phase noise is −91.4 dBc/Hz with 10 MHz offset at 294.2 GHz. The integrated QVCO-mixer consumes a dc power of 167.5 mW.

Modeling technology of InP heterojunction bipolar transistor for THz integrated circuit

AbstractIndium phosphide (InP)‐based transistors play an important role in high‐speed circuit and high‐frequency analog circuit applications. Over the past few decades, terahertz heterojunction bipolar transistor (HBT) is increasingly developed. As a result, many reports of HBTs operating at terahertz region have flourished. Since the high‐frequency circuit design faces the challenge from the lack of precise transistor models, this paper reviews the development of high‐frequency modeling technologies of InP HBT at terahertz region. Processes in the development of small‐signal models at terahertz frequencies, precise parasitic parameters extraction method, improvements in measurement, and the de‐embedding technologies open up more opportunities for precise representation of InP HBTs. Finally, some excellent terahertz circuits based on InP HBT are reviewed.

IMDD Transmission at Net Data Rate of 333 Gb/s Using Over-100-GHz-Bandwidth Analog Multiplexer and Mach–Zehnder Modulator

We demonstrate intensity-modulated direct-detection optical transmission at a record-high data rate with single wavelength and single polarization. The high data rate is achieved with simple optics by using electronic and electrooptic devices with large operation bandwidths. We use a digital-preprocessed analog-multiplexed digital-to-analog converter with a >100-GHz analog multiplexer (AMUX) to drive an 80-GHz Mach–Zehnder optical modulator (MZM). The AMUX is based on 0.25-μm-emitter-width InP heterojunction bipolar transistor technology, and the MZM has InP n-i-p-n heterostructure optical waveguides with capacitance-loaded travelling-wave electrodes. We employ discrete multi-tone modulation controlled by a margin-adaptive bit-loading algorithm. In the experiment, the signal was transmitted over a 20-km dispersion-compensated single-mode fiber link and received by a single photodiode followed by a digital signal processor including a nonlinear equalizer. At a gross bit rate of 400 Gb/s, the bit error rate of the received signal was below the threshold of 20% overhead soft-decision forward error correction code. This result corresponds to a net data rate of 333 Gb/s.