InP Double Heterostructure Bipolar Transistors Research Articles

Composite-Collector InGaAs/InP Double Heterostructure Bipolar Transistors with Current-Gain Cutoff Frequency of 242 GHz

To eliminate the conduction band spike at the base-collector interface, an InP/InGaAs double heterostructure bipolar transistor (DHBT) with an InGaAsP composite collector is designed and fabricated using the conventional mesa structure. The DHBT with emitter area of 1.6 × 15 μm2 exhibits current-gain cutoff frequency ft = 242 GHz at the high collector current density Jc = 2.1 mA/μm2, which is to our knowledge the highest ft reported for the mesa InP DHBT in China. The breakdown voltage in common-emitter configuration is more than 5 V. The high-speed InP/InGaAs DHBT with high current density is very suitable for the application in ultra high-speed digital circuits.

InP DHBT-Based Monolithically Integrated CDR/DEMUX IC Operating at 80 Gbit/s

In this paper, a monolithically integrated clock and data recovery (CDR) circuit with 1:2 demultiplexer (DEMUX), which is intended for use in 80 Gbit/s optical fiber links, is presented. The integrated circuit (IC) is manufactured using an in-house InP double heterostructure bipolar transistor (DHBT) technology, exhibiting cut-off frequency values of more than 220 GHz for both fT and fmax. The CDR circuit in the topology of a phase-locked loop (PLL) is mainly composed of a half-rate linear phase detector including a 1:2 demultiplexer (DEMUX), a loop filter, and a voltage-controlled oscillator (VCO). Hence, the corresponding architecture of each of these components as well as the applied circuit design technique are extensively addressed. Concerning the performance achieved by the CDR/DEMUX IC, the recovered and demultiplexed 40 Gbit/s data from an 80 Gbit/s input signal feature clear eye opening with a signal swing as high as 600 mVpp. The extracted 40 GHz clock signal shows a phase noise as low as -98 dBc/Hz at 100 kHz offset frequency. The corresponding rms jitter amounts to 0.37 ps while the peak-to-peak jitter is as low as 1.66 ps. At a single supply voltage of -4.8 V, the power consumption of the full CDR/DEMUX IC amounts to 1.65 W. To the authors' best knowledge, this work demonstrates the first CDR circuit at the achieved data rate, regardless of all the competing semiconductor technologies

Surface Recombination Currents in “Type-II” NpN InP–GaAsSb–InP Self-Aligned DHBTs

Surface recombination effects are studied in non-passivated non-self-aligned and self-aligned NpN InP-GaAsSb-InP double heterostructure bipolar transistors (DHBTs) down to submicrometer emitter dimensions, and over current densities ranging from 10 A/cm/sup 2/ to 100 kA/cm/sup 2/. The present study is motivated by the drive to scale InP DHBTs for higher speeds and integration densities. Self-aligned InP-GaAsSb-InP DHBTs are characterized by weak emitter size effects (ESEs), and periphery recombination currents are found to be very nearly identical to published results for InP-GaInAs SHBTs despite the major differences in emitter junction band alignments ("type-II" versus "type-I") and injection mechanisms (thermal versus hot electron injection). The correspondence of measured periphery currents in both systems indicates that ESEs are dominated by a mechanism common to InP-GaAsSb and InP-GaInAs devices: this requirement is fulfilled by the direct electron injection from the InP emitter mesa sidewalls onto the extrinsic base surface. Consideration of band alignments and surface depletion effects at the extrinsic base surface is used to explain the commonality of emitter size effects in InP-GaAsSb and InP-GaInAs devices.

Electrical stress damage reversal in non-passivatedfully self-aligned InP HBTs by ozone surface treatment

The authors report that the degradation of device characteristics due to electrical stressing in non-passivated fully self-aligned InP-based heterostructure bipolar transistors (HBTs) can be reversed by a simple surface treatment in ozone. The technique is demonstrated on MOCVD-grown InP/GaAs0.51Sb0.49/InP double heterostructure bipolar transistors (DHBTs) with a C-doped base, and on conventional MBE-grown InP/Ga0.47In0.53As single heterostructure bipolar transistors (SHBTs) with a Be-doped base. This is the first report of the reversibility of bias stress damage in the extrinsic region of III-V HBTs: the experiments presented confirm that stress damage occurs at the exposed emitter periphery, thus explaining the success of emitter ledge passivation techniques.

DC and temperature dependent characteristics of InP double heterostructure bipolar transistors with quaternary collector

The Letter reports the first study of the temperature dependence of the DC characteristics of InP-based double heterostructure bipolar transistors which have a quaternary collector. The quaternary layer was spaced away from the base-collector junction to improve the HBT characteristics. The devices exhibited useful gain over seven orders of magnitude of current and had breakdown voltages of 8 V. The DC gain decreased with decreasing temperature whereas the ideality factors increased.

High-speed InGaAs(P)/InP double-heterostructure bipolar transistors

Double-heterostructure InGaAs(P)/InP bipolar transistors ranging in emitter size from 5 × 10 to 100 × 150 µm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> have been fabricated using a non-self-aligned technology. These transistors exhibit current gains as high as 275 independent of emitter perimeter-to-area ratio. The best frequency of unity current gain was measured in the smallest devices to be 18 GHz. The high-frequency operation was mainly limited by the emitter charging time.