InP-based Heterojunction Bipolar Transistors Research Articles

The effects and mechanisms of 2 MeV proton irradiation on high bias conditions of InP/InGaAs DHBTs

In this work, a 2 MeV proton irradiation experiment has been carried out on self-fabricated InP/InGaAs heterojunction bipolar transistors (HBTs) with fluence of 5 × 1013 H+/cm2 and 1 × 1014 H+/cm2. The degradation and mechanisms have systematically been studied under different bias conditions. The irradiated InP-based HBTs have suffered more sever degradation at low and high bias voltages with larger damage coefficient of current gain (Kβ), due to the increased base recombination current and the slacken collector current respectively. Under high injection current densities, the slow-down of collector current and the collapse of current gain (β) have occurred at increasingly smaller biases as irradiation fluence increases. Consistently, the ideality factor of base current collapses to 1 at high injection current, moreover, the collapse point decreases as fluence increases. The aggravated degradation at high current densities is attributed to the influence of heterojunction barrier effect (HBE) by the structure of the multi-layer collector region. The study would be of great significance for optimizing the device structure and improving the irradiation tolerance.

(Invited) Integration of InP Heterojunction Bipolar Transistors on Silicon Substrates for 6G Networks

The fast expansion of the global datasphere creates a huge demand on the future wireless communication technologies. Although 5G, the 5th generation of the cellular network technology, is still being rolled out, the potential of 6G is already intensively explored. The vision of 6G implies not only massive connectivity and higher data rate (up to 100 Gb/s and more) in ultra-reliable low-latency communication, but machine-to-machine interaction will dominate over those involving humans. AI (artificial intelligence) and machine learning will be omnipresent.6G network will address a frequency spectrum beyond 100 GHz, which provides wider bandwidths and, therefore, potentially simpler modulation schemes and eventually lower power consumption. However, a clear disadvantage of these mm-waves or sub-THz frequencies are the atmospheric absorption and blockage effect by physical obstacles or rain. These challenges must be tackled by a sufficiently high transceiver device density per area together with advanced beam steering and AI empowered networks.The power amplifier (PA) is one of the most critical components of the RF front-end module. Here, InP based heterojunction bipolar transistors (HBT) clearly outperform PAs based on CMOS or SiGe BiCMOS concerning saturated output power, energy efficiency and breakdown voltage. However, the limiting downside of InP HBTs is the missing cost-efficient and scalable fabrication, which hampers its adoption in high-volume 6G applications. In this paper we review various InP HBT fabrication concepts with the aim of lowering the production costs and maintaining high device performance.The best HBT device performance is demonstrated for the lattice-matched deposition on native small-diameter (≤ 150 mm) InP substrates due to perfect III-V crystal quality. Although device fabrication on these wafers cannot profit from the advanced tool park available in 200/300 mm fabs, the main drawbacks are the high cost and brittleness of InP substrates. Realizing InP HBTs on Si substrates allows to benefit from their robustness, low cost, and the access to a mature device fabrication on large-diameter wafers.In wafer reconstitution, numerous diced InP wafer tiles, which already contain the grown HBT layer stack, are bonded to a Si carrier to populate the wafer surface. After planarization, the reconstructed Si wafer can be further fabricated in a CMOS compatible 200/300 mm fab. In transfer printing a comparable approach is followed while only the active device stack is transferred to the Si carrier. Transferring only a thin InP layer to the Si carrier, which serves as a starting surface for the HBT deposition, leads to a so-called engineered substrate. Compared to the previous transfer methods, the III-V device deposition is carried out after bonding. The key advantage of all these heterogenous integration concepts is the access to a CMOS compatible and scalable device fabrication while maintaining the high III-V crystal quality. Nevertheless, the HBT production costs can only be significantly reduced with a certain re-usability of the InP substrates.The monolithic deposition directly on Si substrates would be the most cost-efficient integration approach. Unfortunately, the mismatch in lattice constant and thermal expansion coefficient between Si and III-V materials leads to the formation of relaxation defects, which degrade the HBT device performance. The growth of thick strain relaxation buffers allows to reduce the defect density in the device layers but bears new challenges such as wafer warpage or III-V crack formation.Nano-ridge engineering (NRE) is based on selective area growth (SAG) applying trench-patterned Si wafers. The III-V deposition starts inside very narrow trenches to achieve efficient aspect ratio trapping (ART) of misfit defects. After the trench is filled with III-V material, the growth is continued to engineer a broad and pristine nano-ridge (NR) which holds the device stack. A second oxide pattern prevents sidewall deposition around the NRs during the deposition of the HBT heterolayers.In the first part of this paper, pros, and cons of the most common InP HBT integration scenarios as summarized in figure will be compared in detail. Among all concepts, NRE holds the potential of being the most cost-efficient integration approach due to SAG in line with very limited III-V material deposition. However, the key open question is what NR crystal quality, and hence, device performance can be realized. This question will be addressed in the second part of the paper, reporting about the latest developments at imec. Figure 1

(Invited) Integration of InP Heterojunction Bipolar Transistors on Silicon Substrates for 6G Networks

The power amplifier (PA) in an RF front-end module operating above 100 GHz required for 6G wireless networks is the most power-hungry device circuit component. In that respect, InP-based heterojunction bipolar transistors (HBT) clearly outperform other PA technologies, but being processed on small size wafers, they lack a cost-effective fabrication for mass production. This paper presents a comprehensive comparison of various integration approaches for InP-based HBTs. A key aspect in achieving high yield device fabrication is the use of large-diameter silicon wafers. This study discusses the advantages and disadvantages of different InP-based HBT integration concepts on Si, emphasizing important factors for upscaling InP technologies. Furthermore, this work introduces nano-ridge engineering (NRE), a novel monolithic III-V integration approach currently being explored at imec, which holds the potential for cost-effective and complementary metal oxide semiconductor (CMOS)-compatible production.

Effect of proton irradiation on interfacial and electrical performance of N+Np+ InP/InGaAs hetero-junction

InP-based hetero-junction bipolar transistors (HBTs) are attractive for various millimeter-wave and terahertz electronics due to their ultrahigh frequency performance. Therefore, the study of their irradiation reliability is extremely urgent. In this work, 2 MeV proton irradiation experiment has been carried out on self-fabricated N+Np+ InP/InGaAs hetero-junction. The degradation mechanisms have systematically been studied after exposure to protons of 5 × 1013 H+/cm2. The voltage range of recombination current at low forward bias has been largely expanded from 0-0.2 V to 0–0.6 V. Furthermore, the interface states properties have been characterized by utilizing the frequency-dependent conductance technique, the interface states density (Dit) has increased from approximately 9.02 × 1012 cm−2 eV−1–1.99 × 1013 cm−2 eV−1 to 9.51 × 1012 cm−2 eV−1–2.00 × 1013 cm−2 eV−1 after irradiation. The study would be great significance for understanding the evolution of proton irradiation on relative devices.

Stacked Common-Base vs Common-Emitter mmWave PA Cells and 68–105 GHz Broadband Asymmetrical PA in 250nm InP HBT

In this paper, we perform a comparative analysis between stacked common-emitter (SCE) and stacked common-base topologies (SCB) for high efficiency and broadband millimeter-Wave (mmWave) power amplifiers (PAs) in 250 nm InP-based heterojunction bipolar transistor (HBT) technology. We propose an analytical approach to design stacked PA cells accounting for complex load impedance and intra-matching between stacked transistors to allow optimal loadpull operation of both the devices in the stack. We demonstrate how SCB cell can allow higher gain, mitigated power and efficiency trade-off and linearity, when compared to more well-established SCE cells at higher mmWave frequencies. The designed SCB and SCE cells achieve a measured gain of 11.8 dB/6dB gain, 33%/34% peak PAE, 16.8%/14.5% PAE at 6-dB back-off, and Psat of 18.7 dBm/19.6 dBm at 90 GHz. The SCB PA demonstrates superior linearity, and achieves an EVM of 2.38% at 11.8-dBm average power supporting 3 Gbps 64-QAM. The SCB PA achieves 17.9-18.9-dBm Psat across 80–110 GHz and is one of the highest efficiency, broadband and linear PAs in W-band using InP technology. Utilizing the PA cells, we demonstrate an asymmetrical broadband power combining circuit for high efficiency combining across a large relatively bandwidth. The PA operates across a 68–105 GHz <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{sat,3dB}$ </tex-math></inline-formula> bandwidth with 21.5 dBm peak saturation power and 24% peak PAE.

Cap-layer and charge sheet effect in InP based pnp δ-doped heterojunction bipolar transistor

The effect of varying the cap layer and the δ doped charge sheet has been investigated for an InP based heterojunction bipolar transistor (HBT) using the SILVACO TCAD tool. At the outset the simulation method is validated by comparing with experimental reported results. The InGaAs cap layer is then replaced with InGaAsP. The device figures- of-merit are observed to be remarkable improved with the quaternary cap layer. Some of the noteworthy results include increase in DC current gain from 50 to 126 and the Early voltage is improved from 7.96 V to 19.23 V. The minimum noise figure is reduced from 7.3 to 3 dB. The unity gain cut-off frequency (fT) and the maximum frequency of oscillation (fmax) are improved from 7.3 MHz to 5.4 GHz and 1.59–12.33 GHz respectively. Now in the presence of InGaAsP cap layer the δ-doped charge sheet is varied from 2 × 1011 cm−2 to 2 × 1012 cm−2, and it is observed that it has little effect on these parameters except that the VCE,offset voltage decreases with increase in the sheet density.

Feasibility Study of Wafer-Level Backside Process for InP-Based ICs

This paper reports wafer-level backside process technology, established with the intent to ensure stable operation of InP ICs in the submillimeter wavelength band, which generally suffer from ground bounce and substrate resonance. Our process consists of thinning a 3-in InP wafer, forming dense vias with interval cooling steps, backside metallization with single-level wiring and crack-free dicing. We investigate the effects of the backside process on InP-based heterojunction bipolar transistors and high electron mobility transistors. The results show that the backside process contributes to stable operation up to the 300-GHz range without any degradation of transistor characteristics.

ウェハボンディングプロセスを用いたInP系ダブルヘテロ接合バイポーラトランジスタの熱抵抗低減技術に関する検討

ウェハボンディングプロセスを用いたInP系ダブルヘテロ接合バイポーラトランジスタの熱抵抗低減技術に関する検討

(Invited) Monolithic Integration of III-V As- and P-Based Devices on Si through Direct MBE Growth and Using Lattice Engineered Substrates

Mainstream silicon (Si) CMOS technology is finally experiencing limitations of pure Si-based material and process. For digital electronics, to extend Moore’s law, the industry increasingly is investigating alternative materials and technologies to enhance channel transport properties and reduce power dissipation for future generation transistor circuitry. Heterogeneous integration of compound III-V semiconductor devices on Si may realize high performance integrated circuits for analog and digital applications and can incorporate optoelectronic components for high-speed data transfer. Such integration provides the combined advantages of high volume production of Si-based electronic circuitry with superior high-speed performance of III-V components. At IQE, we developed molecular beam epitaxy (MBE) growth processes for the production of high quality III-V based transistor structures monolithically integrated onto CMOS-compatible substrates by direct MBE growth on Si wafers and also by utilization of specialized Si-on-Lattice-Engineered-Substrate (SOLES) substrates. Through work with industry partners, IQE has grown InP-based high electron mobility transistor (HEMT) and quantum well field effect transistor (QWFET) structures directly on Si substrates by MBE. Following a high-K gate dielectric fabrication process, QWFET devices demonstrated high transconductance of 1750μS/μm and high drive current of 0.49mA/μm at VDS=0.5V. [1] As part of a program funded by the US Defense Advanced Research Projects Agency, IQE developed a direct MBE growth approach of an InP-based heterojunction bipolar transistor (HBT) structure on the SOLES substrates, and together with our collaborators successfully created clusters of high-speed III-V HBT circuitry monolithically integrated side-by-side with Si CMOS on the same wafer. [2] In this paper, we will discuss structural and electronic properties of epitaxial device material, including dislocation filtering in the mismatched metamorphic buffers, and compare performance of devices fabricated on Si with reference material grown on lattice-matched InP substrates. [1] Radosavljevic, M.; Chu-Kung, B.; Corcoran, S.; Dewey, G.; Hudait, M. K.; Fastenau, J. M.; Kavalieros, J.; Liu, W. K.; Lubyshev,D.; Metz, M.; Millard, K.; Mukherjee, N.; Rachmady, W.; Shah, U.; Chau, R. (2009), IEDM Tech. Dig., p.13.1. [2] W. K. Liu, D. Lubyshev, J. M. Fastenau, Y. Wu, M. T. Bulsara, E. A. Fitzgerald, M. Urteaga, W. Ha, J. Bergman, B. Brar, W. E. Hoke, J. R. LaRoche, K. J. Herrick, T. E. Kazior, D. Clark, D. Smith, R. F. Thompson, C. Drazek, and N. Daval, J. Crystal Growth, 311, 1979 (2009).

A simple method for forming compositionally graded InxGa1−xAs1−ySby base of double-heterojunction bipolar transistors modulating CBr4-doping-precursor flow in metalorganic chemical vapor deposition

We studied a CBr4-flow-modulation method as a way of simplifying the formation of a compositionally graded InxGa1−xAs1−ySby base of InP-based heterojunction bipolar transistors (HBTs) by metalorganic chemical vapor deposition. An investigation of C-doping in InxGa1−xAs1−ySby revealed that In and Sb contents decrease as the supply ratio of CBr4 to group-III (RC) increases. We fabricated 0.25-µm-emitter HBTs with a compositionally graded InxGa1−xAs1−ySby base formed by varying RC at constant group-III, group-V, and V/III ratios. By this method, we obtained higher current-gain cut-off frequency (504 GHz) and maximum-oscillation frequency (328 GHz) than those of uniform-InxGa1−xAs1−ySby-base HBTs with the same base/collector thicknesses.

MOCVD-grown compressively strained C-doped InxGa1−xAs1−ySby with high-In/Sb content for very low turn-on-voltage InP-based DHBTs

We investigated metalorganic chemical vapor deposition of C-doped high-In-and-Sb-content compressively strained InxGa1−xAs1−ySby and examined InP-based heterojunction bipolar transistors (HBTs) with low base-emitter turn-on voltage. By lowering the growth temperature to 530°C, the etching effect of CBr4 is suppressed, which is consistent with the results of thermodynamic calculations. We obtained high hole concentration of mid-1019cm−3 with the In content of over 0.20. The base-emitter voltage (VBE) at collector current density (JC) of 10nA/μm2 of large-area HBTs with the high-In-and-Sb-content compressively strained InxGa1−xAs1−ySby base is lower than those of the HBTs with a tensile strained InxGa1−xAs1−ySby or GaAs1−ySby base, owing to the reduction of the band gap of the base layer. We fabricated InP/In0.20Ga0.80As0.55Sb0.45/InP HBTs with a 0.25-μm-wide emitter and obtained the VBE of 0.66V at JC of 1mA/μm2. At JC=13mA/μm2, the device exhibits peak current-gain cut-off frequency of over 400GHz, which is comparable to the value for GaAs1−ySby-base HBTs with the same base and collector thicknesses.

Carbon doping in InGaAsSb films on (001) InP substrate using CBr4 grown by metalorganic chemical vapor deposition

This paper reports on carbon (C) doping in InGaAsSb grown on (001) InP substrates by the metalorganic chemical vapor depositions (MOCVD) method using carbontetrabromide (CBr4). The influence of the CBr4 flow rate on the relationships between InGaAsSb alloy compositions and the molar flow ratio of III–V-atom precursors was investigated in C-doped InGaAsSb films. We found that there is nonlinear dependence of the solid In content on the molar flow ratio of group-III precursors for C-doped InGaAsSb. Thermodynamic calculations of the reactions in the InGaAsSb growth process reveal that the characteristic nonlinear dependence is due to the etching reactions of group-III elements with hydrogen bromide, which is generated by CBr4 decomposition. The solid Sb content of both undoped and C-doped InGaAsSb films decreases with increasing molar flow ratio of In precursors due to the preferential incorporations of InAs in In-rich antimonide compounds. On the basis of the obtained knowledge, we have succeeded in growing C-doped InGaAsSb film with a high hole concentration of over 1.0×1019cm−3, which is useful for the base layer of InP-based heterojunction bipolar transistors. As in C-doped GaAsSb, the effect of hydrogen passivation of C-acceptors in C-doped InGaAsSb is almost negligible.

Selective area growth of InAs on InP with dielectric mask

Low resistance ohmic contacts are important for high frequency applications of InP-based heterojunction bipolar transistors and high electron mobility transistors. In this paper, the authors investigate the use of an InAs layer as the low-resistance ohmic contact to these heterostructure devices. Selective area crystal growth of InAs on a dielectric [benzocyclobutene (BCB) polymer] covered InP(100) was carried out by molecular beam epitaxy (MBE). Additionally, direct growth of InAs on InP substrates was performed to allow comparisons with InAs grown on BCB-covered InP. Different growth temperatures were tested to optimize the crystal quality of the InAs layer, which was characterized by scanning electron microscope and x-ray diffraction. Heavy doping of InAs using Te was carried out to determine the lowest sheet resistance. As the substrate temperature was increased from 210 to 350 °C, the crystallinity improved from a polycrystal layer to a single crystal layer with corresponding improvement of surface morphology. Moreover, sharp x-ray diffraction indicated the 3.3% lattice-mismatch was fully relaxed without misorientation. However, a trade off was reached around 290 °C between crystallinity and optimized dopant incorporation of Te into InAs for lowest sheet resistance. The results indicate the potential of Te-doped InAs as emitter contact for high frequency devices by MBE.

Influence of Built-In Drift Fields on the Performance of InP-Based HBTs Grown by Solid-Source MBE

The versatility of solid-source molecular beam epitaxy for the growth of InP/InGaAs heterojunction bipolar transistors (HBTs) is provided by its excellent control of doping and composition grading profiles in combination with its efficiency for carbon doping. Various designs using doping grading or composition grading in the base are investigated to provide a built-in quasi-electric held that enhances electron transport. All graded-base devices exhibit higher current gains (β), as compared to uniform-base structures, but the β improvements are found to be nonproportional to the generated built-in drift fields. The best performances are obtained with a 9% linear composition grading profile. As compared to conventionally grown uniform-base structures, the linearly graded-base HBTs show higher current gains (up to 42%), which is of particular importance particularly in analog and mixed-signal applications.

Low-Turn-on-Voltage Heterojunction Bipolar Transistors with a C-Doped InGaAsSb Base Grown by Metalorganic Chemical Vapor Deposition

We demonstrate the low-turn-on-voltage InP-based heterojunction bipolar transistors (HBTs) with a C-doped InGaAsSb base grown by metalorganic chemical vapor deposition. As the solid In content of InGaAsSb increases, not only the near-band-edge emission peak energy in photoluminescence spectra of the InGaAsSb film but also the turn-on base–emitter voltage of the HBT with an InGaAsSb base decrease. These results are attributed to the reduction of the InGaAsSb band gap with the increase of solid In content. We obtain the turn-on voltage of 0.35 V at collector current density of 1 A/cm2 in the HBT with a In0.22Ga0.78As0.73Sb0.27 base, which is one of the lowest turn-on voltages ever reported.

Ultrahigh-Speed Low-Power DACs Using InP HBTs for Beyond-100-Gb/s/ch Optical Transmission Systems

This paper presents the circuit designs and measured performance of two ultrahigh-speed low-power 6-b digital-to-analog converters (DACs) using InP-based heterojunction bipolar transistors (HBTs) for beyond-100-Gb/s/ch optical transmission systems. The first design is based on an R-2R ladder-based current-steering architecture with a novel double-sampling technique that relaxes the speed restraints for the DAC and helps achieve ultrahigh-speed operation. The DAC with the double-sampling technique achieves an excellent sampling speed of up to 32 GS/s with low power consumption of 1.4 W. The second design is based on a new timing alignment technique. The DAC with the timing alignment technique operates at a sampling rate of 28 GS/s with very low power consumption of 0.95 W and achieves an excellent figure of merit (0.53 pJ per conversion step). It provides a clear multilevel modulated signal for QAM transmission and can be applied to beyond-100-Gb/s/ch optical transmission systems.

Trends in Submicrometer InP-Based HBT Architecture Targeting Thermal Management

More than ever, thermal management in InP-based heterojunction bipolar transistors (HBTs) is a critical issue since high junction temperature degrades transport properties and device reliability. This paper presents investigation results on the impact of device architecture enhancements aimed at reducing thermal resistance using alternative substrates or passivation materials or metallic collectors or all of them. Using 3-D scalable technology computer-aided design electrothermal simulations, the impact of these features is quantified. This prospective work is based on calibration measurements performed on InP bulk HBTs with various InGaAs subcollector thickness values. A wafer-bonded Si-substrate, a 25-nm-thin InGaAs subcollector, and SiN passivation are the key technological features that reduce the thermal resistance by 70%. An even more aggressive thermal management architecture using metallic collectors reduces the thermal resistance up to 80%.

InP-based heterojunction bipolar transistors with InGaAs/GaAs strained-layer-superlattice

In this paper, we report the design, fabrication, and characterization of an InP/InGaAs heterojunction bipolar transistor (HBT) employing a lattice-mismatched In0.53Ga0.47As/GaAs strained-layer-superlattice (SLS) base structure. The performance of the SLS-base device is also compared with that of an In0.53Ga0.47As uniform-base structure. The digitally graded-base devices exhibit a slightly lower gain at low bias voltage and a higher current gain at high currents. While the offset voltage remains comparable in the two structures, the graded-base InP/InGaAs HBTs, with built-in fields of ∼66 kV/cm, have typically a maximum dc current gain of 18% larger than that of transistors with uniform base.

Crystallographic orientation effects on the performance of InP-based heterojunction bipolar transistors

We report the crystallographic orientation effects in InP-based heterojunction bipolar transistors (HBTs). The DC and RF characteristics of DHBTs fabricated on the same wafer were found to be dependent on the emitter orientation. Self-aligned InP/InGaAs DHBTs with [0 1 −1] emitter direction exhibit higher current gains, more stable and also better RF performance, while maintaining similar breakdown voltages, as compared to [0 1 1] oriented devices. Most of the differences are attributed to the resulting emitter–base sidewall profiles obtained after mesa etching. Without ruling out piezoelectric and stress effects, generally observed in III–V based HBTs, a contribution to the orientation effect, especially on the DC characteristics seem to be related to the more effective extrinsic base passivation for the [0 1 −1] orientation. For a given bias point, the maximum oscillation frequency ( f max) is also slightly higher in [0 1 −1] oriented devices, due to a smaller base resistance resulting from a smaller base–emitter spacing, while the cut-off frequency ( f T) remains comparable in both orientations.

InP/InGaAs heterojunction bipolar transistors with different μ-bridge structures

Several μ-bridge structures for InP-based heterojunction bipolar transistors (HBTs) are reported. The radio frequency measurement results of these InP HBTs are compared with each other. The comparison shows that μ-bridge structures reduce the parasites and double μ-bridge structures have a better effect. Due to the utilization of the double μ-bridges, both the cutoff frequency fT and also the maximum oscillation frequency fmax of the 2 × 12.5 μm2 InP/InGaAs HBT reach nearly 160 GHz. The results also show that the μ-bridge has a better effect in increasing the high frequency performance of a narrow emitter InP HBT.