Transputer Research Articles

The transputer - an effective tool for geometric modelling systems

Experience has shown that computing machines with conventional bus–structured architectures suffer a degradation in performance due to bus contention after typically three to five processors are placed on the system. The transputer and the programming language Occam2 have introduced low–cost parallel processing. The design of the transputer is such that for certain applications the addition of more transputers gives a corresponding linear increase in computing power. It has been shown that computer graphics is such an application. The transputer allows very powerful networks to be built up relatively cheaply and extended as finances allow with very few changes to the program code being necessary. This paper investigates the implications of using the transputer for a geometric modelling system. It outlines the facilities offered by the transputer, its B007 graphics board and the programming language Occam2, before presenting the experience of the authors in using these to implement geometric modelling systems based on wire–line and spatial enumeration modelling.

Static and dynamic low-congested interval routing schemes

Interval routing schemes (IRS) have been extensively investigated in the past years with special emphasis on shortest paths. Besides their theoretical interest, IRS have practical applications, as they have been implemented with wormhole routing in the last generation of INMOS transputer router chips. In this paper we consider IRS that are optimal with respect to the congestion of the induced path system. In fact, wormhole routing is strongly influenced by the maximum number of paths that share a physical link and from low to moderate congestion it outperforms the packet switching technique. We provide a general framework able to deal with the various congestion issues in IRS. In fact, we will distinguish between static cases, in which the source–destination configurations are fixed, and dynamic cases, where they vary over time. All these situations can be handled in a unified setting, thanks to the notion of competitiveness introduced in this paper. We first give some general results not related to specific traffic demands. Then, in the one-to-all communication pattern, we show that constructing competitive IRS for a given network is an intractable problem, both for the static and the dynamic case, that is when the root vertex is fixed and when it can change along the time, respectively. Finally, both for one-to-all and all-to-all communication patterns, we provide nicely competitive k-IRS for relevant topologies. Networks considered are chains, trees, rings, chordal rings and multi-dimensional grids and tori. We consider both the directed congestion case, in which there are pairwise opposite unidirectional links connecting two neighbor processors, and the undirected congestion case, in which two neighbors are connected by a single bi-directional link.

The Rationale for Distributed Semantics as a Topology Independent Embedded Systems Design Methodology and its Implementation in the Virtuoso RTOS

Virtuoso VSP is a fully distributed real-time operating system originally developed on the Inmos transputer. Its generic architecture is based on a small but very fast nanokernel and a portable preemptive microkernel. It was further on ported in single and virtual single processor implementations to a wide range of processors. This paper describes the rationale for developing the distributed semantics of Virtuoso's microkernel and describes some of the implementation issues. The analysis is based on the parallel DSP implementations as these push the performance limits most for hard real-time applications. Extensions of the model towards heterogeneous embedded target systems are discussed.

Parallel Database Techniques

Parallel Database Techniques

Parallel implementations of numerical simulation of wind flow around buildings

In this work, two parallel implementation strategies for the numerical simulation of wind flow around buildings were developed based on a four-processor transputer system. The first parallel strategy is based on the functional decomposition of the problem. It is easily implementable, but the degree of parallelism is low. In the second strategy, both the functional and the domain parallelisms of the problem were utilized, so the degree of parallelism is highly increased. Numerical examples indicate that the parallel speed-ups and efficiencies achievable by the second strategy are significantly greater than those of the first one.

Deadlock-free interval routing schemes

k-Interval labeling schemes (k-ILS) are compact routing schemes on general networks which have been studied extensively and recently been implemented on the latest generation INMOS Transputer Router chips. In this paper, we introduce an extension of the k-ILS to the (k, s)-DFILS (deadlock-free ILS), where k is the number of intervals and s is the number of buffers used at each node or edge to prevent deadlock. Whereas k-ILS only compactly represents shortest paths between pairs of nodes, this new extension aims to represent those particular ones that give rise also to deadlock-free routing controllers which use a low number of buffers per node or per edge. In particular, we consider deadlock-free routing controllers obtained using a standard deadlock prevention technique (acyclic orientation coverings) which can be applied both to packet and wormhole routing. While both time and space complexity results are given for general networks, tight results are shown for specific topologies, such as trees, rings, grids, complete graphs, and chordal rings. Moreover, trade-offs are derived between the number of intervals k and the number of buffers s in (k, s)-DFILS for hypercubes, grids, tori, and Cartesian products of graphs.

Multidimensional interval routing schemes

Interval routing scheme ( k-IRS) is a compact routing scheme on general networks. It has been studied extensively and recently been implemented on the latest generation INMOS Transputer Router chip. In this paper we introduce an extension of the Interval Routing Scheme k-IRS to the multidimensional case 〈 k, d〉-MIRS, where k is the number of intervals and d is the number of dimensions. Whereas k-IRS only represents compactly a single shortest path between any two nodes, with this new extension we are able to represent all shortest paths compactly. This is useful for fault-tolerance and traffic distribution in a network. We study efficient representations of all shortest paths between any pair of nodes for general network topologies, for product graphs and for specific interconnection networks such as rings, grids, tori, hypercubes and chordal rings. For these interconnection networks we show that for about the same space complexity as k-IRS we can represent all shortest paths in 〈 k, d〉-MIRS (as compared to only a single shortest path in k-IRS). Moreover, trade-offs are derived between the dimension d and the number of intervals k in multidimensional interval routing schemes on hypercubes, grids and tori.

A Matlab Toolbox for Simulating Transputer and Digital Signal Processors Applications

The performance demands of modem control and signal processing systems is increasing beyond the capacity of conventional sequential processors, requiring parallel processing solutions to satisfy the real-time requirements.In this paper a new version of Matlab toolbox for simulating homogeneous systems built with Inmos transputers or digital signal processors is presented. This toolbox extended the capabilities of a previous approach. Its development aims to help the designer to compare, effortlessly, the performance of alternative parallel solutions, and also to monitor the program execution, within each processing node.This simulator is under further development to extend its applicability to parallel heterogeneous systems.

Performance Evaluation of Heterogeneous Architectures

An investigation into the performance evaluation of heterogeneous architectures is presented in this paper. A task allocation strategy for maximum efficiency is proposed and evaluated. Compiler efficiency and code optimisation are also investigated in context of performance of an architecture. An adaptive filtering algorithm and a beam simulation algorithm are considered. These are implemented on a heterogeneous architecture incorporating the TMS320C40 digital signal processing devices, the Intel i860 vector processor and the T805 Inmos transputers.

A modular computing architecture for autonomous robots

This paper presents a modular computing architecture used for intelligent control of autonomous robots. The architecture takes the form of multiple sensing and control layers, based on Locally Intelligent Control Agents (LICAs) in which IBM PowerPC, SIEMENS 80C166, and INMOS Transputers are adopted. The control tasks are distributed among a set of the LICA-based behaviour experts that tightly couple sensing and action, but which are also loosely coupled to each other. It provides a high bandwidth computing platform for real-time navigation and control tasks embedded in real-world applications. Based on this modular design, autonomous mobile robots have been built successfully to implement both indoor and outdoor navigation.

A scalable multibus configuration for connecting transputer links

The paper presents the development and the performance of a novel bus based message passing interconnection scheme which can be used to join a large number of INMOS transputers via their serial communication links. The main feature of this architecture is that it avoids the communication overhead which occurs in systems where processing nodes relay communications to their neighbors. It also produces a flexible and scalable machine whose attractive characteristics are its simplicity and low latency for large configurations. We show that this architecture is free from deadlock, exhibits much smaller latency than most directly connected transputer networks and has a scalable bandwidth, in contrast to other bus topologies.

On the Hardness of Devising Interval Routing Schemes

The k-Interval Routing Scheme (k-IRS) is a compact routing scheme on general networks. It has been studied extensively and recently been implemented on the latest generation of the INMOS transputer router chips. In this paper we investigate the time complexity of devising a minimal space k-IRS and we prove that the problem of deciding whether there exists a 2-IRS for any network G is NP-complete. This is the first hardness result for k-IRS where k is constant and the graph underlying the network is unweighted. Moreover, the NP-completeness holds also for linear and strict 2-IRS.

Non-linear Optimization on a Parallel Intel i860 RISC Based Architecture

A description of a parallel implementation of the Genetic Algorithm for non-linear optimization is presented. The system is implemented with four Intel i860 RISC processors using INMOS transputers for communications. The performance is compared to the Cray Y-MP, Cray J916, an SGI Power Challenge L R8000 75 MHZ workstation, an SGI Challenge L R4400 100 MHZ work-station, an SGI Indy SC R4400 200 MHZ workstation, and both parastation and Paramid parallel I860 machines, each with one to four participating I860s. Comparisons were made for neural network optimization of a limited dependent variable problem and a chaotic time series. A complex rational expectations model was also estimated. The I860 based machines were able to achieve performances comparable to the supercomputers.

A computer network based control architecture for autonomous distributed multirobot systems

This paper presents the specification and implementation procedure using a microcomputer network based autonomous distributed control architecture for industrial multirobot systems. The procedure is based on the concept of data flow network controlled by communicating sequential processes to perform coordinated tasks. Robots and other computerized industrial devices such as conveyors and manufacturing machines are defined as object-oriented Petri nets. A modular and hierarchical approach is adopted to define a set of Petri net type diagrams which represent concurrent activities of control processes for such devices. Asynchronous and synchronous interactions are modelled by places and transitions, respectively, in global process interaction nets. The control software is implemented on a computer network using Inmos transputers with true parallel processing and message passing primitives efficiently handled in hardware. Petri net based models are directly and efficiently transformed to corresponding codes in occam, the high level parallel programming language defined for the transputer.

A family of parallel QR factorization algorithms

Rapid computation of the QR factorization of a matrix is fundamental to many scientific and engineering problems. The paper presents a family of algorithms parameterized by the number of processors available P, arithmetic grain aggregation parameters g1, g2, …, gP, and communication grain aggregation parameter h, which computer the QR factorization of a matrix A ∈ Cm × n with minimal latency. The approach is particularly well suited for dedicated distributed memory architectures such as linear arrays of INMOS Transputers, Texas Instruments C40s or Analog Devices 21060s.

Multi-layer perceptron based modelling of nonlinear systems

This paper develops the area of nonlinear modelling based on the nonlinear function approximation capabilities of the multi-layer perceptron network. The mechanism of this nonlinear modelling technique is explained in a novel yet straightforward manner. Important aspects such as model order, over-parameterisation and the choice of excitation signals are discussed. In order to provide familiar and useful model structures techniques are provided through which a trained neural model can be expanded to provide Volterra or polynomial NARX expressions. Likewise it is shown that linearisation of the network at each sample can generate the parameters for use with an adaptive linear plant model. In order to accelerate the training of the multi-layer perceptron, both full-memory and memoryless versions of the Broyden-Fletcher-Goldfharb-Shanno (BFGS) training algorithm are developed. A novel network pruning algorithm is provided that utilises the Hessian matrix generated by the full-memory BFGS algorithm. A parallel version of the memoryless BFGS algorithm is developed and mapped efficiently onto a pipeline of INMOS transputers. The performance of this parallel algorithm is demonstrated for the training of an inferential model for a realistic continuously-stirred-tank-reactor system. Finally, these neural modelling techniques are applied to provide an accurate predictive model of viscosity for an industrial polymerisation reactor.

Parallel computation of configuration space

SUMMARYMany motion planning methods use Configuration Space to represent a robot manipulator's range of motion and the obstacles which exist in its environment. The Cartesian to Configuration Space mapping is computationally intensive and this paper describes how the execution time can be decreased by using parallel processing. The natural tree structure of the algorithm is exploited to partition the computation into parallel tasks. An implementation programmed in the occam2 parallel computer language running on a network of INMOS transputers is described. The benefits of dynamically scheduling the tasks onto the processors are explained and verified by means of measured execution times on various processor network topologies. It is concluded that excellent speed-up and efficiency can be achieved provided that proper account is taken of the variable task lengths in the computation.

Advanced motion control of mechatronic systems via a high-speed dsp and a parallel processing transputer network

A system for implementing an advanced motion controller using a floating-point digital signal processor (DSP) and a transputer-based parallel processing system is presented. The discussion includes a brief look at the advantages of using DSPs in real-time control applications and the architecture for integrating DSPs with parallel processing transputer networks to enhance computing power. The main focus of this paper is on the design of a system that combines the Texas Instruments TMS320C30 floating-point DSP with a parallel processing system based on Intel i860 RISC processors and Inmos transputers to achieve excellent real-time response and superior computational power. The software of the system is hosted in the popular MATLAB program which furnishes a simple user interface and programming environment. The system is ideal for implementing advanced motion control experiments that require high-speed floating-point computations as well as fast sampling rates. In addition to real-time experiment, the system also includes a simulation package to allow rapid verification of the user's program and control algorithm. A complex adaptive motor control experiment is presented to illustrate the application of the system.

Expert Self-Tuning Control for an Automatic Voltage Regulator

The practical application of adaptive controllers requires the addition of substantial supervision strategies in the form of jacketing software. An elegant approach introduces an expert system to perform all monitoring functions, creating a distinction between the identification and control algorithms. A self-tuning automatic voltage regulator has been established on an industry standard VME platform linked to a network of Inmos transputers. Test results on a 3 kVA laboratory micromachine system are presented, illustrating how the performance and robustness of the adaptive controller can be greatly enhanced through expert system intervention

Expert control of a self-tuning automatic voltage regulator

The practical implementation of self-tuning controllers normally requires the incorporation of substantial monitoring/jacketing software schemes. By introducing an expert system to perform such duties, a distinction can be made between control and identification algorithms, and their associated supervisory functions. The adaptive controller has been established on an industry-standard VME platform linked to a network of Inmos transputers. Illustrations are given of how the performance and robustness of the self-tuning automatic voltage regulator can be significantly improved, through expert-system intervention, on a 3-kVA laboratory micromachine system.