In-loop Deblocking Filter Research Articles

A Video Steganalytic Approach Against Quantized Transform Coefficient-Based H.264 Steganography by Exploiting In-Loop Deblocking Filtering

This article presents a method for detection of H.264 steganographic algorithms that modulate quantized transform coefficients (QTCs) for data hiding. The in-loop deblocking filter specified in the H.264 standard is used for attenuating the discontinuities at coded block boundaries. However, our investigation indicates that the deblocking filtering process would probably be affected by QTC modification. Therefore, we suggest performing steganalysis by considering the influence of QTC modification on filtering decisions and filtering operations. In the filtering of luma block edges, for each luma sample, we try to obtain the cumulative amount of modification applied to it caused by filtering operations, and determine the frequency of the modification made to its sample value. Based on this, a 768-dimensional feature set is designed for training and classification. Extensive experiments were conducted under a range of setups to evaluate the effectiveness of the proposed method. The corresponding experimental results demonstrate that, compared with the prior art, our proposed method is generally capable of providing superior performance on detecting QTC modification in H.264 video, even at low embedding strengths.

Adaptive deblocking method for low bitrate coded HEVC video

HEVC in-loop deblocking filter significantly improves the subjective quality of coded video by removing blocking artifact. However, there are still visible blocking artifacts in the complex videos with fast and chaotic motions coded at a low bitrate. In this paper, we propose a three-step deblocking filter scheme, which pre-processes video to remove undesired noise, next removes the corner outliers, and then suppresses the normal blocking artifacts with adaptive deblocking filters. The whole deblocking filtering process is applied on both luma and chroma components. Experimental results show that the proposed method could effectively improve the subjective quality for various videos, and outperform other typical post-processing deblocking methods.

HEVC Deblocking Filter

This paper describes the in-loop deblocking filter used in the upcoming High Efficiency Video Coding (HEVC) standard to reduce visible artifacts at block boundaries. The deblocking filter performs detection of the artifacts at the coded block boundaries and attenuates them by applying a selected filter. Compared to the H.264/AVC deblocking filter, the HEVC deblocking filter has lower computational complexity and better parallel processing capabilities while still achieving significant reduction of the visual artifacts.

Performance, Analysis of Filtering Schedule Using Deblocking Filter for the Reduction of Block Artifacts from MPEQ Compressed Document Images

Problem statement: The visual effects of blocking artifacts can be reduce by using deblocking filter. Also with out smoothing the natural edges,the perceived quality of video sequence can be enchanced. This study propose a method to remove blocking artifacts in low bit-rate block based video coding. Approach: The proposed algorithm has two separate filtering modes, which are selected by pixel behavior around the block boundary. In each mode, proper one-dimensional filtering operations are performed across the block boundary along horizontal and vertical directions, respectively. In the first mode corresponding flat regions, a strong filter is applied inside the block as well as on the block boundary, because the flat regions are more sensitive to the Human Visual System (HVS) and the artifacts propagated from the previous frame due to motion compensation are distributed inside the block. In the second mode corresponding to other regions, a sophisticated smoothing filter, which is based on the frequency information around block boundaries, is used to reduce blocking artifacts adaptively without introducing undesired blur. Even though the proposed deblocking filter is quite simple, it improves both subjective and objective image quality for various image features. Results and Conclusion: Deblocking filter improves the PSNR of about 0.1 dB for video encoded using MPEG-4 and H.264 without using its own in-loop deblocking filter. It has proven to be good in the reduction of the very annoying blocking artifacts caused by video compression.

High efficiency data access system architecture for deblocking filter supporting multiple video coding standards

This paper presents an efficient VLSI architecture of in-loop deblocking filter (ILF) with high efficiency data access system for supporting multiple video coding standards including H.264 BP/MP/HP, SVC, MVC, AVS, and VC-1. Advanced standards, such as H.264 MP/HP, SVC, and MVC, adopt Macro Block Adaptive Frame Field (MBAFF) to enhance coding efficiency which results in the performance bottleneck of deblocking filter due to complex data access requirement. This design challenge has not been discussed in previous works according to our best knowledge. Therefore, we develop a Prediction Data Management (PDM) to manage the input prediction data order of deblocking filter for different coding types (like frame/field) and multiple standards. We also design an extended output frame buffer module to solve the system bus architecture restriction (like 1K boundary and burst length) and achieve high efficiency data access by using MB-based scan order. By using these techniques, we can solve the data accessing design challenge and reduce 67% bus latency. After being implemented by using 90 nm CMOS technology, the proposed work can achieve real-time performance requirement of QFHD (3840×2160@30fps) when operated at 156MHz at the cost of 50.6K gates and 2.4K bytes local memory. The maximum operating frequency of the proposed design, i.e. 370MHz, is higher than the required real-time operating frequency so that voltage scaling may be adopted to reduce power consumption.

Improved total variation minimization method for compressive sensing by intra-prediction

Total variation (TV) minimization algorithms are often used to recover sparse signals or images in the compressive sensing (CS). But the use of TV solvers often suffers from undesirable staircase effect. To reduce this effect, this paper presents an improved TV minimization method for block-based CS by intra-prediction. The new method conducts intra-prediction block by block in the CS reconstruction process and generates a residual for the image block being decoded in the CS measurement domain. The gradient of the residual is sparser than that of the image itself, which can lead to better reconstruction quality in CS by TV regularization. The staircase effect can also be eliminated due to effective reconstruction of the residual. Furthermore, to suppress blocking artifacts caused by intra-prediction, an efficient adaptive in-loop deblocking filter was designed for post-processing during the CS reconstruction process. Experiments show competitive performances of the proposed hybrid method in comparison with state-of-the-art TV models for CS with respect to peak signal-to-noise ratio and the subjective visual quality.

Methods for depth-map filtering in view-plus-depth 3D video representation

Abstract View-plus-depth is a scene representation format where each pixel of a color image or video frame is augmented by per-pixel depth represented as gray-scale image (map). In the representation, the quality of the depth map plays a crucial role as it determines the quality of the rendered views. Among the artifacts in the received depth map, the compression artifacts are usually most pronounced and considered most annoying. In this article, we study the problem of post-processing of depth maps degraded by improper estimation or by block-transform-based compression. A number of post-filtering methods are studied, modified and compared for their applicability to the task of depth map restoration and post-filtering. The methods range from simple and trivial Gaussian smoothing, to in-loop deblocking filter standardized in H.264 video coding standard, to more comprehensive methods which utilize structural and color information from the accompanying color image frame. The latter group contains our modification of the powerful local polynomial approximation, the popular bilateral filter, and an extension of it, originally suggested for depth super-resolution. We further modify this latter approach by developing an efficient implementation of it. We present experimental results demonstrating high-quality filtered depth maps and offering practitioners options for highest-quality or better efficiency.

Low power architecture design and hardware implementations of deblocking filter in H.264/AVC

An adaptive in-loop deblocking filter (DF) is standardized in H.264/AVC to reduce blocking artifacts and improve compression efficiency. This paper proposes a low power DF architecture with hybrid and intelligent edge skip filtering order. We further adopt a four-stage pipeline to boost the speed of DF process and the proposed Horizontal Edge Skip Processing Architecture (HESPA) offers an edge skip aware mechanism for filtering the horizontal edges that not only reduces power consumption but also reduces the filtering processes down to 100 clock cycles per macroblock (MB). In addition, the architecture utilizes the buffers efficiently to store the temporary data without affecting the standarddefined data dependency by a reasonable strategy of edge filtering order to enhance the reusability of the intermediate data. The system throughput can then be improved and the power consumption can also be reduced. Simulation results show that more than 34% of logic power measured in FPGA can be saved when the proposed HESPA is enabled. Furthermore, the proposed architecture is implemented on a 0.18μm standard cell library, which consumes 19.8K gates at a clock frequency of 200 MHz, which compares competitively with other state-of-the-art works in terms of hardware cost.

Wireless transmission of HD video using H.264 compression over UWB channel

With the technological advancement, entertainment has become revolutionized and the high-definition (HD) video has become an integral feature of our modern amusement system. The demand for wireless transmission of HD video is rapidly rising for its ubiquitous nature, easy installation and relocation. Such wireless transmissions of HD video streams require very high bandwidth. The ultra-wideband (UWB) offers a large bandwidth, and short-range high-speed data transmission at low cost and low power consumption. In this paper, we present the feasibility study to transmit HD video wirelessly using H.264/AVC compression over the UWB communication channel. Simulations are carried out by controlling key H.264/AVC encoder parameters such as, in-loop deblocking filter, group of pictures, and quantization parameter. Based on the analysis, an optimum setting of these parameters is proposed for different bandwidth requirements, as well as acceptable video quality. The bandwidth achieved is restricted between 1.5 and 20 Mbps with a minimum reconstruction quality of 34 dB. The HD bit stream is then transmitted over the UWB communication channel and the demonstration shows that the overall encoder performance is satisfactory with the transmission bit-error-rate (BER) in the range of 10−5–10−8.

Variable block-based deblocking filter for H.264/AVC on low-end and low-bit rates terminals

H.264/AVC supports variable block motion compensation, multiple reference frames, 1/4-pixel motion vector accuracy, and in-loop deblocking filter, compared with previous video coding standards. While these coding techniques are major functions for video compression improvement, they lead to high computational complexity at the same time. For the H.264 video coding techniques to be actually applied on low-end/low-bit rates terminals more extensively, it is essential to improve the coding efficiency. Currently the H.264 deblocking filter, which can improve the subjective quality of video, is hardly used on low-end terminals due to computational complexity. In this paper, we propose an enhanced method of deblocking filter that efficiently reduces the blocking artifacts occurring during the low-bit rates video coding. In the ‘variable block-based deblocking filter (VBDF)’ proposed in this paper, the temporal and spatial characteristics of moving pictures are extracted using the variable block-size information of motion compensation, the filter mode is classified into four different modes according to the moving-picture characteristics, and the adaptive filtering is executed in the separate modes. The proposed VBDF can reduce the blocking artifacts, prevent excessive blurring effects, and achieve about 30–40% computational speedup at about the same PSNR compared with the existing methods.

H.264 Deblocking Speedup

This letter tackles the problem of reducing the complexity of H.264 decoding. Since deblocking accounts for a significant percentage of H.264 decoding time, our focus is on the H.264 in-loop deblocking filter. Observing that branch operations are costly and that in the deblocking process there are events with significantly high probability of occurrence, we regroup and simplify the branch operations. We apply the idea of Huffman tree optimization to speed up the boundary strength derivation and the true-edge detection by taking advantage of the biased statistical distribution. Our analyses and experiments show that the proposed techniques can reduce the deblocking computation time typically by a factor of more than seven times, while maintaining the bit-exact output.

Analysis and Efficient Architecture Design for VC-1 Overlap Smoothing and In-Loop Deblocking Filter

In contrast to the macroblock-based in-loop deblocking filters, the filters of VC-1 perform all horizontal edges (for in-loop filtering) or vertical edges (for overlap smoothing) first and then the vertical edges (for in-loop filtering) or horizontal edges (for overlap smoothing) within a frame, field, or slice. These two filters of VC-1 perform filtering operations on many edges among reconstructed blocks in different processing orders. The entire procedure is very time-consuming and involves high memory access loading for the whole system. This paper analyzes the behavior of VC-1 filters and presents several efficient methods and an integrated architecture design, which involves an overlapped 12times12 block that combines overlap smoothing with in-loop filtering for performance and cost by sharing circuits and system resources. In order to go a step further to efficiently utilize system resources, this paper also presents two other efficient methods, multiple processing order and modified chrominance processing order, which greatly reduce external memory cycles and on-chip memory size for filtered and temporal reconstructed pixels. The specification of the proposed architecture implemented with TSMC 90-nm multithreshold voltage technique has capability to process HDTV1080p 30-fps video and HDTV 2048 t 1536 24-fps video at 200 MHz. The same concept is applicable to other video processing algorithms, especially in deblocking filter for video post-processing in a frame-based order.

Design of Vector Register Architecture in DSP Processor for Efficient Multimedia Processing

In this paper, we present an efficient instruction set architecture using vector register file hardware to accelerate operation of general matrixvector operations in DSP microprocessor. The technique enables in-situ row-access as well as column access to the register files. It can reduce the number of memory access significantly. The technique is especially useful for block-based video signal processing kernels such as FFT/IFFT, DCT/IDCT, and two-dimensional filtering. We have applied the new instruction set architecture to in-loop deblocking filter processing in H.264 decoder. Performance comparisons show that the required load/store operations for the in-loop deblocking filter can be reduced about 42%. The architecture would improve the processing speed, and code density in DSP microprocessor especially for video signal processing substantially.

A performance optimized architecture of deblocking filter for H.264/AVC

The in-loop deblocking filter is one of the complex parts in H.264/AVC. It has such a large amount of computation that almost all the pixels in all the frames are involved in the worst case. In this paper, a fast deblocking filter architecture is proposed, and it can effectively save the operating time. In the proposed architecture, two 1-D filters are introduced so that the vertical filtering and the horizontal filtering can be performed at the same time, Only 120 cycles are needed for a macroblock. Our architecture is also a memory efficient one, and only one 4x4 pixels register, one 4x4 transpose array and one 16x32 b two-port (SRAM) are used as buffers in the filtering process. The simulation and synthesis results show that, with almost the same or even smaller area than some 1-D filter based architectures before, the proposed one can save more than 40% processing time. The architecture is suitable for real-time applications and can easily achieve the requirement of processing real-time video in 1080HD (high definition format, 1 920x1 088@30 fps) at 100 MHz.

ASIP Approach for Implementation of H.264/AVC

This paper presents an Application Specific Instruction Set Processor (ASIP) for implementation of H.264/AVC, called Video Specific Instruction-set Processor (VSIP). The proposed VSIP has novel instructions and optimized hardware architectures for specific applications, such as intra prediction, in-loop deblocking filter, integer transform, etc. Moreover, VSIP has coprocessors for computation intensive parts in video signal processing, such as inter prediction and entropy coding. The proposed VSIP has much smaller area and can dramatically reduce the number of memory access compared with commercial DSP chips, which result in low power consumption. Moreover, the proposed hardware accelerators have small size, consume low power consumption, and thus, they can support real-time video processing. VSIP has been thoroughly verified using an FPGA board having the Xilinx? Virtex II. VSIP can implement a real-time H.264/AVC decoder. The proposed VSIP is one of promising solutions for video signal processing.

Deeply pipelined DSP solution to deblocking filter for H.264/AVC

The in-loop deblocking filter in H.264/AVC contains highly adaptive on both sample level and block edge level, which inevitably appears in the loop kernel of the algorithm. Therefore it is quite difficult to efficiently implement the filter on digital signal processor (DSP) platform. In this paper, deeply pipelined DSP solutions to both edge filter and boundary strength decision are presented. To avoid conditional jumping when performing edge filter, DSP first calculate all possible filtered outputs, then combine them with corresponding masks to get single output for each sample, and last conditionally store the combined output based on the final content activity check result. Moreover, on the basis of the symmetry of filtering on both sides of the edge, two symmetrical samples are packed into one register for pair processing to increase the parallelism of the pipeline. While for boundary strength decision, two-pass pipelines are designed. In the first pass, strengths are created by using the inter-relative information on block level, and then in the second pass, these strengths are refined based on the intra mode checks on macroblock level. To cooperate with global filter control and also to keep pipelining, a two-level internal memory organization is presented as well. The simulated results indicate that this efficient implementation can support real-time filtering for high resolution videos

A Pipelined Hardware Implementation of In-loop Deblocking Filter in H.264/AVC

In this paper we present a pipelined hardware implementation of in-loop deblocking filter in H.264/AVC. A pipelined datapath has been adopted to boost the speed of the deblocking filter process. The processing order of the filter is rearranged to facilitate the deblocking of the pixels in a pipelined fashion. A suitable buffer mechanism has also been proposed that reduces the size of the on-chip SRAM and redundant external memory accesses. The hardware implementation, under TSMC 0.13 /spl mu/m standard cell library, consumes only 7.5 K gates at a clock frequency of 200 MHz. Our architecture supports real-time deblocking of high resolution (2048/spl times/1024) video applications at 30 fps over three channels.