In-line Wafer Inspection Research Articles

Patterning approach for detecting defect in device manufacturing

Compact handheld devices which were a dream in the past are now a reality; this has been enabled by miniaturization of circuit architectures including power devices. Scaling down of the design feature sizes does come with a price with an increase in systematic defects during chip manufacturing. There are generally two methods of inline defect detection adopted to monitor the semiconductor device fabrication—optical inspection and electron beam inspection. The optical inspection uses ultra-violet and deep ultra-violet (UV/DUV) light to find patterning defects on the wafer. While the electron-beam inspection uses electron charge and discharge measurement to find electrical connection defects, both are a costly procedure in terms of resources and time. The physical limit of feature resolution of the optical source is now making the defect inspection job difficult in miniaturized application specific integrated circuit (ASIC). This study is designed to test the patterning optimization approach on both inspection platforms. Using hotspot analysis weak locations are identified in the full chip design, and then they are verified in the inline wafer inspection. The criterion for hot-spot determination is also discussed in this paper.

Patterning approach for detecting defect in device manufacturing

Compact handheld devices which were a dream in the past are now a reality; this has been enabled by miniaturization of circuit architectures including power devices. Scaling down of the design feature sizes does come with a price with an increase in systematic defects during chip manufacturing. There are generally two methods of inline defect detection adopted to monitor the semiconductor device fabrication --- optical inspection and electron beam inspection. The optical inspection uses ultra-violet and deep ultra-violet (UV/DUV) light to find patterning defects on the wafer. While the electron- beam inspection uses electron charge and discharge measurement to find electrical connection defects, both are a costly procedure in terms of resources and time. The physical limit of feature resolution of the optical source is now making the defect inspection job difficult in miniaturized application specific integrated circuit (ASIC). This study is designed to test the patterning optimization approach on both inspection platforms. Using hotspot analysis weak locations are identified in the full chip design, and then they are verified in the inline wafer inspection. The criterion for hot-spot determination is also discussed in this paper. DOI: 10.21883/FTP.2017.12.45192.8203

In-line metrology of nanoscale features in semiconductor manufacturing systems

Quality control and defect monitoring are of great importance to the semiconductor industry. This article presents a system to enable inspection of nanoscale features in-line with nanomanufacturing processes. The ultimate goal of this research is to integrate this metrology system into current semiconductor manufacturing processes to enable true in-line wafer inspection and quality control. In the system presented in this paper, AFMs that have been shrunk down on to a single MEMS chip are used to scan the surface of a sample. A flexure-based mechanism allows the MEMS-based AFM to be positioned over a millimeter range of motion, with nanometer level precision when properly actuated. The performance of the system in areas such as positioning repeatability, AFM stability and measurement resolution are evaluated in this study. Owing to the small size of single-chip AFM (1 million times smaller than a conventional AFM instrument), it is a good candidate for multipoint detection. Overall, the system presented in this paper significantly shortens inspection time and dramatically decreases the setup time required for an AFM to load, approach, and measure a sample making in-line inspection of nanoscale features in semiconductor manufacturing systems feasible.

The SEM in present-day semiconductor FABS

Computers, cars, HDTV, and microwave ovens: what great modern conveniences! Why do these marvels of technology work the way they do? The Scanning Electron Microscope has a lot to do with it. For the last decade, the shrinking geometries of integrated circuits have necessitated the use of the Scanning Electron Microscope (SEM) for inspection and metrology. The current device feature sizes in production are as small as 0.5μm, and current feature sizes under development are 0.25μm or smaller. The semiconductor industry depends on the SEM to tell us if our processes, whether production or developmental, are correct. Neither leading edge fabs nor developmental fabs could function very well without the SEM.The uses of the SEM are many and varied, both inside and outside the fab. Inside the fab, there are many inspection steps to be performed. Although the optical microscope is still a viable option for, and is still routinely used for, in-line wafer inspection, the SEM is indispensable for inspection (Fig. 1) of small geometries such as 0.35μm lines and spaces and 0.5μm contact holes.