Patterning approach for detecting defect in device manufacturing

Abstract

Compact handheld devices which were a dream in the past are now a reality; this has been enabled by miniaturization of circuit architectures including power devices. Scaling down of the design feature sizes does come with a price with an increase in systematic defects during chip manufacturing. There are generally two methods of inline defect detection adopted to monitor the semiconductor device fabrication—optical inspection and electron beam inspection. The optical inspection uses ultra-violet and deep ultra-violet (UV/DUV) light to find patterning defects on the wafer. While the electron-beam inspection uses electron charge and discharge measurement to find electrical connection defects, both are a costly procedure in terms of resources and time. The physical limit of feature resolution of the optical source is now making the defect inspection job difficult in miniaturized application specific integrated circuit (ASIC). This study is designed to test the patterning optimization approach on both inspection platforms. Using hotspot analysis weak locations are identified in the full chip design, and then they are verified in the inline wafer inspection. The criterion for hot-spot determination is also discussed in this paper.