Injection-locked Frequency Tripler Research Articles

A 60 GHz Injection-Locked Frequency Tripler With Spur Suppression

A 60 GHz injection-locked frequency tripler is designed to improve spectral purity with spur suppression of the fundamental and the even-order harmonics. Several circuit designs are utilized in the harmonic current injection circuit to maximize the third-order harmonic and minimize the undesired harmonic current outputs, including notch filters and a capacitive cross-coupled transistor pair. With the input signal of 0.5 dBm at 19.7 GHz, the harmonic rejection ratios of the fundamental, and the second-order achieve 31.3 dBc, and 45.8 dBc, respectively. Implemented in 0.13 m CMOS technology, the core circuit consumes power of 9.96 mW with 1.2 V supply voltage. The entire die occupies an area of 985 × 866 μm2.

Injection‐locked frequency tripler with series‐tuned resonator in 0.13 μm CMOS technology

AbstractThis article proposes a CMOS LC‐tank injection locked frequency tripler (ILFT) fabricated in 0.13 μm CMOS process and describes the circuit design, operation principle and measurement results of the ILFT.The differential input/output ILFT circuit is realized with a first‐harmonic injection‐locked oscillator (ILO) stacked in series on two transconductance amplifiers used as a third harmonic generator. The first‐harmonic ILO with a series‐tuned LC resonator amplifies the signal from the third harmonic generated transconductance amplifier. At the supply voltage of 0.75 V, the free‐running frequency of the ILO is from 9.14 GHz to 9.40 GHz. At the incident power of 0 dBm, the total locking range is from the incident frequency 2.95 GHz to 3.43 GHz. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 1107–1110, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25101