Initial Acquisition Time Research Articles

지상파 클라우드 방송 시스템을 위한 초기 타이밍 획득 알고리즘

In this paper, we propose an initial timing acquisition algorithm for terrestrial cloud transmission (CTxn) systems. By combining auto-correlations of several repetition patterns within preamble symbols, the proposed scheme can improve the reliability of the timing metric for CTxn system with co-channel interferences. Simulation results show that the proposed scheme improves the reliability of the timing metric for terrestrial CTxn systems.

DS-UWB 시스템에서 송신 필터에 따른 초기 동기 획득 성능 비교

본 논문에서는 DS-UWB 시스템에 사용되는 송신 필터에 따른 초기 동기 획득 성능을 모의 실험을 통해 비교하고, 칩 레이트가 1.32 Gchip/s인 DS-UWB 디지털 송신기에서 interpolation factor가 4인 제곱근 코사인 필터를 적용한 경우와 구형 필터를 적용한 경우 DS-UWB 수신기의 초기 동기 획득 성능은 AWGN 채널 환경뿐만 아니라 CM1/CM3 채널 환경하에서도 비슷한 성능을 냄을 실험을 통해 살펴 본다. 또한, 55 MHz의 시스템 클럭으로 동작하는 24 병렬 처리 상관 연산기 및 동기 획득기 구조에 대해 설명하고 초기 동기 획득 방법을 기술한다. 본 논문에서는 DS-UWB 시스템 설계시 구형 송신 필터를 사용하여 1.32 Gsample/s D/A 변환기 및 A/D 변환기를 적용할 수 있게 함으로써 DS-UWB 칩셋 개발시 현실적으로 고려할 수 있는 솔루션을 제시한다. In this paper, we compare the performance of initial timing acquisition in direct sequence ultra-wideband(DS-UWB) systems with different transmit pulse shaping filters through extensive computer simulations. Simulation results show that the timing acquisition performance of the DS-UWB system, whose chip rate is 1.32 Gchip/s, employing a rectangular transmit filter is similar to that employing a square root raised cosine(SRRC) filter with an interpolation factor of 4 in the realistic UWB channels(CM1 and CM3) as well as the additive white Gaussian noise(AWGN) channel. Additionally, we present both a 24-parallel digital correlator structure and a 24-parallel processing searcher operating at a 55 MHz system clock, and then briefly discuss the initial timing acquisition procedure. Because we can adopt an 1.32 Gsample/s digital-to-analog(D/A) converter and an 1.32 Gsample/s analog-to-digital(AID) converter in the DS-UWB system by employing the rectangular transmit filter, we have a realistic solution for the DS-UWB chipset development.

Initial Timing Acquisition for Binary Phase-Shift Keying Direct Sequence Ultra-wideband Transmission

This paper presents a parallel processing searcher structure for the initial synchronization of a direct sequence ultra-wideband (DS-UWB) system, which is suitable for the digital implementation of baseband functionalities with a 1.32 Gsample/s chip rate analog-todigital converter. An initial timing acquisition algorithm and a data demodulation method are also studied. The proposed searcher effectively acquires initial symbol and frame timing during the preamble transmission period. A hardware efficient receiver structure using 24 parallel digital correlators for binary phase-shift keying DS-UWB transmission is presented. The proposed correlator structure operating at 55 MHz is shared for correlation operations in a searcher, a channel estimator, and the demodulator of a RAKE receiver. We also present a pseudo-random noise sequence generated with a primitive polynomial, 1+ x 2 +x 5 , for packet detection, automatic gain control, and initial timing acquisition. Simulation results show that the performance of the proposed parallel processing searcher employing the presented pseudorandom noise sequence outperforms that employing a preamble sequence in the IEEE 802.15.3a DS-UWB proposal.

Preamble Boosted Power Based Frame Timing Acquisition Algorithm for Cellular OFDMA Systems

We propose a simple initial frame timing acquisition algorithm for cellular OFDMA systems. The proposed algorithm utilizes the 9dB boost in preamble power set by the IEEE 802.16e standard. Simulation results show that the proposed algorithm succeeds in acquiring the starting point of a frame under not only single cell but also multi-cell environments, while the conventional autocorrelation-based method fails under multi-cell environment.

Fast Acquisition Clock and Data Recovery Circuit With Low Jitter

This paper presents a half-rate clock and data recovery circuit (CDR)that combines the fast acquisition of a phase selection (PS) delay-locked loop (DLL) with the low jitter of a phase-locked loop (PLL). The PLL acquisition time improves considerably with use of a phase frequency magnitude detector(PFMD) that feeds back an estimate of the magnitude of the frequency difference in addition to the sign. Measurements in 0.5/spl mu/m CMOS technology show operation up to 700 Mb/s, a 7% acquisition range, an initial acquisition time of 8 bit times with jitter of 30% bit time, and jitter of 16 ps after the PLL acquires lock. With a phase frequency detector (PFD), the PLL locks in about 700 ns from an initial frequency difference of 7%. Measurements using a PFMD show the 700 ns PLL acquisition time is reduced on average by about a factor of 5 to 140 ns from an initial 7% frequency difference. The power dissipation is 300mW.

Initial synchronization of DS-CDMA via bursty pilot signals

We consider initial timing acquisition in discrete-sequence code-division multiple-access (DS-CDMA) when propagation is affected by multipath and fading, and where the base-station broadcasts a synchronization pilot signal in the form of bursts of modulated chips transmitted periodically and separated by long silent intervals. Subject to certain simplifying assumptions, we derive the maximum-likelihood (ML) estimator by solving a constrained maximization problem. Our ML timing estimator has constant complexity per observation sample. The relation to other estimation methods is addressed, and performance comparisons are provided by simulation. The proposed estimator yields good performance independently of the multipath-intensity profile of the channel, provided that the delay spread is not larger than a given maximum spread. Moreover, our estimator is fairly robust to the mismatch in the fading Doppler spectrum and provides good performance for both fast and slow fading.

A decision-directed symbol timing recovery circuit for ATSC digital TV receivers

We present and analyze a full-digital decision-directed symbol timing recovery circuit based on the double-sampling maximum-likelihood estimator. Intended for the ATSC digital TV system, the proposed scheme works independently of the segment synchronization by extracting timing information from the randomized data symbols even in the extremely small roll-off case. With the proposed method we get not only quick synchronization, but also robust timing recovery with reduced timing jitter compared to the conventional correlation method. The simulation is performed using the 8-level PAM signal, and evaluated in terms of the steady-state timing jitter under AWGN and multipath ghost channels. Additionally, initial timing acquisition and segment synchronization performance are also shown.

Dual-loop DPLL gear-shifting algorithm for fast synchronization

Since most digital phase-locked loops (DPLL's) used in digital data transmission receivers require both fast acquisition of input frequency and phase in the beginning and substantial jitter reduction in the steady state, the DPLL loop bandwidth should be adjusted accordingly. In this paper, three bandwidth adjusting (gear-shifting) algorithms are presented, which allow both fast acquisition and significant jitter reduction for each different noise environment and hardware requirement. These algorithms suggest an optimal sequence of control parameters for a dual-loop DPLL which achieves the fastest initial acquisition time by trying to minimize the jitter variance in any given time instant. The algorithms can be used for carrier recovery or clock recovery in mobile communications, local area networks and disk drives that require a short initial preamble period.

Theoretical analysis of M-ary/SS communication systems using racing counters and a Hadamard matrix

The performance of M-ary spread spectrum (M-ary/SS) communication systems is discussed. Firstly, the initial acquisition time is evaluated. Secondly, the retention time, which is the average number of frames holding correct frame timing, and the recovery time, which is the average number of frames required to establish synchronization, are derived. Lastly, the bit-error rate (BER) performance is evaluated. M-ary/SS communication systems, which have more than one spreading code, can improve the BER performance under conditions in which there is additive white Gaussian noise (AWGN). However, the synchronization of M-ary/SS communication systems is difficult because they have several spreading codes. The frame synchronization method uses a Hadamard matrix and "racing counters." As a result, the retention time becomes longer than the recovery time when the size of the lower counter differs greatly from that of the upper counter in the racing counters. Then the BER gets close to the performance which is achieved under complete synchronization.

Synchronization of Noncolocated TV Signals in a Satellite Time-Compression Multiplexing System

We describe here a simple method to synchronize three TV signals originated from noncolocated up-link stations in a satellite Time-Compression Multiplexing (TCM) system. In this system, information in three fields of each TV picture is compressed into a single field time so that the compressed signals from the three sources can be time multiplexed for transmission. The up-link synchronization ensures that the Radio Frequency (RF) bursts from different sources will arrive at the satellite without collision. Our method employs a dynamic master/slave arrangement whereby the first station signing on assumes the role of a master. The other stations subsequently can synchronize their transmissions to the master's by simply monitoring the received RF bursts from the satellite, measuring their respective delays to the spacecraft, and then phase locking their local color subcarrier clocks to the master's transmitted bursts. When the master station stops transmitting, an automatic procedure is provided for the second station to take over as the new master. The worst-case jitter performance is well below 100 ns, and the initial acquisition time can be kept less than one-half second. These are more than adequate for the present TV application, although further improvements are possible if necessary.

Digital filtering and prediction for communications systems time synchronization

A timing subsystem consisting of an <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</tex> -point finite impulse response (FIR) digital differentiator followed by an <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M</tex> -step adaptive linear predictor is described. The techniques may be employed for initial timing acquisition and subsequent resynchronization of ASK, FSK, and PSK digital communications systems employing pilot signals. The overall approach is effective, and provides a new method for solving a most critical problem ultimately affecting the achievable probability of bit-error rate. Various tradeoffs are discussed for selecting the type of digital differentiator, as well as the parameter of both the differentiator and predictor. Performance data is presented for realistic signal-to-noise ratios and digital word sizes. The described method has been implemented as part of a microprocessor-based FSK acoustic telemetry system, and is found to be computationally efficient as well as extremely accurate.