Abstract
Since most digital phase-locked loops (DPLL's) used in digital data transmission receivers require both fast acquisition of input frequency and phase in the beginning and substantial jitter reduction in the steady state, the DPLL loop bandwidth should be adjusted accordingly. In this paper, three bandwidth adjusting (gear-shifting) algorithms are presented, which allow both fast acquisition and significant jitter reduction for each different noise environment and hardware requirement. These algorithms suggest an optimal sequence of control parameters for a dual-loop DPLL which achieves the fastest initial acquisition time by trying to minimize the jitter variance in any given time instant. The algorithms can be used for carrier recovery or clock recovery in mobile communications, local area networks and disk drives that require a short initial preamble period.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
More From: IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.