Abstract
Since most digital phase-locked loops (DPLLs) used in digital data transmission receivers require fast acquisition of input frequency and phase in the beginning and substantial jitter reduction in the steady-state, the DPLL loop bandwidth should be adjusted accordingly. An optimal gear-shifting algorithm which allows very fast acquisition time is presented. This algorithm suggests a sequence of control parameters which achieves the fastest initial acquisition time by trying to minimize the jitter variance (minimum mean squared error: MMSE) in any given time instance. The algorithm can be used for carrier recovery or clock recovery in data modems, local area networks and disk drives that require a very short initial preamble period. >
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