Influence Of Self-heating Effect Research Articles

Impact of self-heating on RF/analog and linearity parameters of DMG FinFETs in underlap and overlap configurations

In this paper, the influence of self-heating effect (SHE) on the performance of Silicon on Insulator (SOI) dual material gate (DMG) FinFETs in underlap and overlap configurations for RF/analog applications is reported using three-dimensional TCAD simulators. The increase in electron velocity at channel surface is due to reduce effective electrical field at drain end, resulting in smaller DIBL and hot carrier effects. The device insights are reported by electron velocity, lattice temperature, thermal resistance, and output conductance versus frequency profiles. The findings on analog/RF figures of merit such as transconductance (gm), output conductance (gd), intrinsic gain (Ai), gate capacitance (Cgg), intrinsic delay (τ), cut-off frequency (fT), transconductance generation factor (TGF), gain frequency product (GFP), transconductance frequency product (TFP), and gain transconductance frequency product (GTFP) are reported with and without SHE. The results show that analog performance of Conventional and Underlap structures are improved but the influence of SHE is more deteriorating on Overlap structure. Furthermore, the linearity performance parameters VIP2, VIP3, IIP3, and 1 dB compression point are degraded with self-heating is due to increase in gm2 and gm3 values. It is seen that the gate overlap structure exhibits higher ON state performance which even after deterioration with Self-heating is still better than its counterparts as it has better gate controllability stemming from its lower effective channel length.

Study on self heating effect of enhancement-mode Ga<sub>2</sub>O<sub>3</sub> vertical MOSFET

<p indent="0mm">In this paper, a vertical enhanced Ga₂O₃ MOSFET is designed. Due to the low thermal conductivity of gallium oxide material, the output characteristics of the device under different crystal orientation materials, different thermal resistance and different temperature are studied. The thermal characteristics of Ga₂O₃ MOSFET are analyzed based on the temperature distribution characteristics of the device. The thermal conductivity model studies the effect of different orientation of gallium oxide on the output characteristics and temperature distribution of the device, and it is found that the thermal conductivity of [010] orientation is the best. When <italic>T</italic>=<sc>300 K,</sc> the thermal conductivity is about <sc>0.1 W/cm K,</sc> which is higher than that of other crystal directions, and the corresponding output saturation current is the largest under the same voltage (<italic>V</italic>_gs=<sc>3 V, </sc><italic>I</italic>_dsat&gt;<sc>400 A/cm²).</sc> Furthermore, the output characteristic curves of different crystal directions under different temperature and different thermal resistance are studied. With the decrease of thermal resistance, the heat dissipation capacity at the device boundary is improved. Thus, the influence of self-heating effect is suppressed and the drain saturation current increases. The normal operation of the device can be ensured when the boundary thermal resistance is <sc>0.01–0.005 cm² K/W.</sc> All of these provide reliable methods and reference value for optimizing device performance in the future.

Investigating the Impact of Self-Heating Effects on some Thermal and Electrical Characteristics of Dielectric Pocket Gate-all-around (DPGAA) MOSFETs

The dielectric pocket gate-all-around (DPGAA) MOSFET is being considered the best suited candidate for ULSI electronic chips because of excellent electrostatic control over the channel. However, the phenomena of self-heating and hot carrier injection (HCI) severely affect the performance of the device, and make the behaviour of the DPGAA FET very unpredictable. In the present article, a comprehensive investigation under the influence of self-heating effects has been done for the variation in the lattice and carrier temperature against spacer length, ambient temperature, device length, and thermal contact resistance including ON and Off currents with gate bias voltage (VGS). In order to analyse the SHEs, the hydrodynamic (HD) and thermodynamic (TD) transport models have been used for three-dimensional (3D) electrothermal (ET) simulation. The Lucky (hot carrier injection) model has been used to study the HCI degradation in DPGAA MOSFET using Sentaurus 3D TCAD simulator.

Optimization of Stacked Nanoplate FET for 3-nm Node

In this article, various characteristics of nanoplate FET were studied based on TCAD simulation for a 3-nm node. The optimum geometry specification was proposed through comparison of RC delay from previous studies. Additionally, the impacts of self-heating effects (SHEs) in the 3-nm node were evaluated in the targeting device because it is expected that highly scaled areas such as channels have a negative effect on the performance due to low heat dissipation. This degradation was verified in a single device and in ring oscillator (RO) operation. pMOS is comparatively stronger than nMOS in terms of SHEs due to wider channel width. In RO operation, the influence of SHEs begins to appear at over 0.65 V through power and speed comparison. Therefore, an operation voltage under 0.65 V can be the optimal voltage to suppress SHEs.

Impact of Geometry, Doping, Temperature, and Boundary Conductivity on Thermal Characteristics of 14-nm Bulk and SOI FinFETs

In this paper, the self-heating effect (SHE) in 14-nm bulk and SOI FinFETs are investigated through the TCAD simulation. To achieve high authoritative evidences, the calibration is performed by ${I} _{\mathrm{ D}}$ - ${V} _{\mathrm{ G}}$ curve fitting based on the experimental data. The main contributions include: 1) The distribution of heat generation and temperature gradient along the channel are disclosed. Two peeks of heat generation are observed in source extension (SE) and drain extension (DE), respectively; 2) The dependence of maximum lattice temperature and thermal resistance on device geometry and parameters including fin width, fin height, length of SE and DE, the thickness of STI and BOX, doping concentration of extension, and gate voltage, are thoroughly analyzed; 3) The influence of SHEs on the electrical characteristic of FinFET under different ambient temperatures are also revealed. Moreover, the critical heat removal paths of bulk and SOI FinFETs are discussed. For the former, most of heat vertically diffuses to the substrate, and then to heat sink, whereas in SOI FinFET it firstly dissipates to source, drain, and gate, and then to heat sink. Finally, several optimization thumbs of SHEs are proposed.

Influence of Self-Heating Effect on I-V Dates of Party Depleted Submicron Silicon-on-Insulator CMOS Transistors at High Ambient Temperatures

To solve the problems of high temperature microelectronics the influence of the self heating effect on the I-V dates partially depleted submicron silicon–on-insulator CMOS transistor in the ambient temperature range from 525 K to 650 K is discussed. Approach consists in combination of experimental data and of computational simulating results. For simulation of electrothermal characteristics of SOI CMOS transistor is considered three-layered structure. Temperature distribution is calculated numerically using iterative algorithm in conjunction with software COMSOL Multiphysics. I-V dates of SOI CMOS transistors are calculated by means of two-dimensional models for n-and p-channel transistors of Sentaurus TCAD developed in the system of instrument and technological modelling. TCAD models are calibrated on experimental characteristics for 525 K. It is shown that with growth of ambient temperature the self-heating mechanism contribution consistently decreases. By results of modeling it is established that self-heating contributions at supply voltages 5.5 V to decreases for n-transistor in 2.8 times, p-transistor in 2.2 times. The relative decline of current n-type transistor for reduced from 11.6% to 5.5% and for p-type with 15% to 9%. However, different dynamics of current recession for n-and p-transistors is significant for analog applications that need to be considered at high-temperature circuit design. The proposed methodology allows to critically assess the contribution of the self-heating mechanism on the I-V dates for a wide range of high temperatures and supply voltages. Underestimating this fact leads to unreasonable values for the maximum temperature and limit of thermal stability for the separate SOI CMOS transistor. In total this can be a prerequisite for a significant simplification of the design of not only the chip construction but also the whole electronic Board.

Influence of Self-Heating Effect on Interface Trap Generation in Highly Flexible Single-Crystalline Si Nanomembrane Transistors.

We analyze the interface trap states generated by the self-heating effect in flexible single-crystalline Si nanomembrane (sc-Si NM) transistors. Despite the excellent device performance (Subthreshold swing: ~61 mV/dec, Ion/off: ~109, Nit: ~5 × 1010 cm-2, µeff: ~250 cm²/V·s) and mechanical flexibility (RB,min ═ 1 mm) of sc-Si NM transistors on a polymer substrate, they are vulnerable to thermal reliability issues due to the poor thermal conductivity (κ < 1 W/m·K) of the polymer substrate. Understanding the detailed mechanism driving heat-related device degradation is key to improving device reliability, life expectancy, and overall device performance. Thus, a charge pumping method was employed to systematically analyze the device degradation caused by the self-heating effect. This enabled the interface trap density to be investigated for the flexible sc-Si NM transistors on a polymer substrate after a bias stress. For comparison, a heat spreading layer (HSL) made using a 1-µm thick Ag film (κ~400 W/m·K) was integrated into the sc-Si NM device to mitigate the self-heating effect. The results showed that the interface trap density was proportional to the self-heating effect. This facilitated the fundamental understanding of the self-heating effect of flexible sc-Si NM transistors, opening a robust route to realizing high performance flexible devices using sc-Si NM.

New Insight Into Negative Bias Temperature Instability Degradation During Self-Heating in Nanoscale Bulk FinFETs

In this letter, we investigate the threshold voltage shift ( $\Delta {V} _{\textsf {th}}$ ) by negative bias temperature instability (NBTI) coupled with the self-heating effect (SHE) in a 14-nm bulk ${p}$ -FinFET. To analyze the effect of NBTI in the presence of the SHE, the DC stress was performed under high-bias conditions, i.e., gate bias ${V}_{\textsf {GS}} = -{1.3}$ V and drain bias ${V}_{\textsf {DS}}$ up to −1.3 V at room temperature, which was usually referred to as hot-carrier degradation (HCD) stress. It has been observed that the long-time (10 s ~ 103 s) power-law time exponent ( ${n}$ ) decreases as ${V}_{\textsf {DS}}$ increases, and ${n}$ was very close to that of NBTI-induced $\Delta {V} _{\textsf {th}}$ rather than HCD-induced $\Delta {V} _{\textsf {th}}$ at ${V}_{\textsf {GS}} = {V}_{\textsf {DS}} = -{1.3}$ V. For the first time, computer-aided design simulations were performed in combination with SHE and NBTI. The effect of NBTI in ${p}$ -FinFET is confirmed to contribute significantly to $\Delta {V} _{\textsf {th}}$ under DC HCD stress because of SHE. The influence of SHE is mitigated in high-frequency circuit operation, but special attention should be paid to NBTI issues due to the potential occurrence of SHE as the technology nodes shrink.

Analysis on Self-Heating Effects in Three-Stacked Nanoplate FET

In this paper, self-heating effects (SHEs) in three-stacked nanoplate FETs were investigated through the TCAD simulation. In order to obtain high reliability, the evaluation of SHEs was performed after ${I}_{D}$ – ${V}_{G}$ curve fitting based on the experimental data. First, general analysis on SHEs was conducted to confirm the influence of SHEs to electrical characteristics. The optimized nanoplate width for great electrical properties was proposed by using the figure-of-merit factor under the consideration of SHEs. In addition, difference of heat flux between FinFET and stacked nanoplate FET was analyzed. Based on the analysis, the two-step thermal resistance ( ${R}_{\text {th}}$ ) model depending on drain voltage was proposed. The two-step ${R}_{\text {th}}$ model in the stacked nanoplate FET matched well with the Berkeley short-channel IGFET model—common multigate model compared the other ${R}_{\text {th}}$ models. A seven-stage ring oscillator with the proposed ${R}_{\text {th}}$ model was demonstrated, and SHEs in the circuit level were confirmed.

I – V characteristics and THz radiation properties of Bi2212 mesas

Large mesa structures composed of intrinsic Josephson junctions (IJJs) are expected to be one of a promising source of THz electromagnetic wave. In order to study the collective dynamics in large mesas with and without the influence of self-heating effect, two types of mesa structures are fabricated. One is a double-mesa structure which enables the non-uniform bias current distribution to examine the heat-flow in large mesas. We find that the current lead geometry strongly affects the collective switching of IJJs into resistive state even if the number of IJJs in the mesas is the same. Another is a standard rectangular mesa structure used in the emission experiments. In this mesa, we observe THz radiation from IJJs biased at the low bias region, where the self-heating effect is almost negligible, on inner branches of multiple I – V structures and find that all of observed intense inner-branch emissions correspond to the same cavity resonance mode.

Investigation of Self-Heating Effect on Hot Carrier Degradation in Multiple-Fin SOI FinFETs

In this letter, the impact of self-heating effect (SHE) on hot carrier degradation (HCD) in multiple-fin silicon-on-insulator (SOI) FinFETs was investigated. First, the ac conductance method has been utilized to extract the thermal resistance ( $\text{R}_{\mathrm {th}}$ ) of SOI FinFETs with different fin numbers. Then, both dc and ac stresses are applied on the gate and drain of transistors with the source grounded to characterize the HCD. It is found that the device with large fin number demonstrates high-temperature rise caused by SHE, which results in the enhanced generation of oxide bulk trapped charges. Thus, the SHE aggravates the HCD significantly. The influence of SHE on HCD is mitigated when the frequency of ac stress is above 10 MHz. Therefore, special attention to the SHE on HCD must be paid for accurate HCD prediction in FinFETs.

New insights into self-heating in double-gate transistors by solving Boltzmann transport equations

Electro-thermal effects become one of the most critical issues for continuing the downscaling of electron devices. To study this problem, a new efficient self-consistent electron-phonon transport model has been developed. Our model of phonon Boltzmann transport equation (pBTE) includes the decay of optical phonons into acoustic modes and a generation term given by electron-Monte Carlo simulation. The solution of pBTE uses an analytic phonon dispersion and the relaxation time approximation for acoustic and optical phonons. This coupled simulation is applied to investigate the self-heating effects in a 20 nm-long double gate MOSFET. The temperature profile per mode and the comparison between Fourier temperature and the effective temperature are discussed. Some significant differences occur mainly in the hot spot region. It is shown that under the influence of self-heating effects, the potential profile is modified and both the drain current and the electron ballisticity are reduced because of enhanced electron-phonon scattering rates.

Theoretical Study of Electron Confinement in Submicrometer GaN HFETs Using a Thermally Self-Consistent Monte Carlo Method

This paper studies various existing advanced GaN heterostructures, which are introduced to provide better confinement of the 2-D electron gas in the channel using a Monte Carlo simulation method coupled with a 3-D solution of the heat diffusion equation. It is shown that the introduction of acceptors in the buffer layer and the introduction of an InGaN back-barrier layer at the bottom of the channel, in a single heterojunction AlGaN/GaN heterostructure field-effect transistor (HFET), improve charge confinement in the channel. It is also shown how the inclusion of an AlGaN carrier exclusion layer at the AlGaN/GaN interface significantly improves the current-handling capability of the HFET. This paper is also a study of the effect of carrier confinement on the thermal performance of each structure; the results show that better confinement of carriers in the HFET channel is accompanied by an enhancement of the influence of self-heating effects.

Theoretical analysis of polarization bistability in vertical cavity surface emitting semiconductor lasers

The polarization bistability of vertical cavity surface emitting lasers under external optical injection is analyzed theoretically. It is found that on the condition where the optical gain is blue-shifted relative to the cavity mode, the bistable characteristics of VCSEL's can be improved significantly: (1) low optical power of the external injection light is required, (2) the influence of self-heating effects is minimized, and (3) wide bistable hysteresis loop width can be maintained. Furthermore, it is also shown that the reflectivity of Bragg reflectors should also be optimized to improve the performance of VCSEL's as bistable switches.