Influence Of Back-gate Bias Research Articles

Effect of Trapped Charge Induced by Total Ionizing Dose Radiation on the Top-Gate Carbon Nanotube Field Effect Transistors

The excellent performance and radiation-hardness potential of carbon nanotube (CNT) field effect transistors (CNTFETs) have attracted wide attention. However, top-gate structure CNTFETs, which are often used to make high-performance devices, have not been studied enough. In this paper, the total ionizing dose (TID) effect of the top-gate structure CNTFETs and the influence of the substrate on top-gate during irradiation are studied. The parameter degradation caused by the irradiation- and radiation-damage mechanisms of the top-gate P-type CNTFET were obtained by performing a Co-60 γ-ray irradiation test. The results indicate that the transfer curves of the top-gate P-type CNTFETs shift negatively, the threshold voltage and the transconductance decrease when TID increases, and the subthreshold swing decreases first and then increases with the increase in TID. The back-gate transistor is constructed by using the substrate as a back-gate, and the influence of back-gate bias on the characteristics of the top-gate transistor is tested. We also test the influence of TID irradiation on the characteristics of back-gate transistors, and reveal the effect of trapped charge introduced by radiation on the characteristics of top-gate transistors. In addition, the CNTFETs that we used have obvious hysteresis characteristics. After irradiation, the radiation-induced trapped charges generated in oxide and the OH groups generated by ionization of the CNT adsorbates aggravate the hysteresis characteristics of CNTFET, and the hysteresis window increases with the increase in TID.

Back-gate bias effect on the linearity of pocket doped FDSOI MOSFET

In this article, we investigate the feasibility of enhancing the linearity Figures of Merit (FoMs) by introducing pocket implant in the source/drain regions of the FDSOI MOSFET with ground plane (GP) under the influence of back-gate bias (VB) effect. The current investigations are carried out using a well calibrated industry standard simulation tool Silvaco ATLAS. The proposed device architecture shows reduction in peak electric field, improvement in effective mobility (μeff), subthreshold slope (SS), threshold voltage (VTH) & off-state current (IOFF) by rearranging the accumulated charges that can mitigate impact ionization. The improvement in these parameters leads to enhanced the fundamental transconductance term (gm) and in turn boosts the linearity, which can make it essential for RF/wireless IC designs. An investigation is performed to figure out the non-linear behaviour of proposed FDSOI MOSFET with pockets design by simulating the DC characteristics. The vital FoMs such as higher order transconductance coefficients, intermodulation distortion (IM) and input intercept point (IIP) are explicitly analysed along with the impact of VB.

The Influence of Back Gate Bias on the OCTO SOI MOSFET’s Response to X-ray Radiation

This work investigates the X-ray irradiation impact on the performance of an on-conventional transistor called OCTO SOI MOSFET that adopts an octagonal gate shape instead of a rectangular. The electrical behaviors of both devices were studied through an experimental comparative analysis of the total ionizing dose influence. In addition, the back-gate bias technique was applied in these devices to reestablish its threshold voltages and drain currents conditions that were degraded due the trapping of positive charges in the buried oxide. As the main finding of this work, after the irradiation procedure, we notice that the OCTO device is capable to reestablish its pre-rad electrical behavior with a smaller back gate bias than the one observed in the standard one counterpart. This is mainly because the parasitic transistors in the bird’s beak region are practically deactivated due the particular octagonal gate geometry.

Accurate modeling of the influence of back gate bias and interface roughness on the threshold voltage of nanoscale DG MOSFETs

An accurate 2-D analytical model regarding the influence of back gate bias Vbg on the threshold voltage of double gate (DG) MOSFETs for a wide range of geometric dimensions and gate materials is presented. The threshold voltage Vt and its variation have been determined with different geometric dimensions taking into account several effects such as quantum mechanical effects and the surface roughness effect for various back gate bias conditions. Our theoretical calculations rely on the solution of 2-D Poisson’s equation while numerical simulation results are obtained from the numerical device simulator ATLAS. The shift in Vt due to quantum effects and the surface roughness-induced effect has been calculated by employing the accurate value of ground state energy computed using variational approach for a finite rectangular quantum well as exists in a real DG MOS structure. Our investigations show that Vt increases with increasing negative Vbg and exhibits significant enhancement due to quantum effects and the surface roughness effect particularly for channel thickness below 5nm. The margin of accuracy has been verified by comparing our analytical and simulation results with reported simulation and experimental data for various devices.

Influence of Back-Gate Bias and Process Conditions on the Gamma Degradation of the Transconductance of MuGFETs

The gamma radiation-induced variation of the transconductance in the subthreshold region is studied for different back-gate voltages and for different kinds of SOI MuGFETs: devices with and without selective epitaxial growth (SEG) and 45 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> rotated transistors. Wide fin devices show a larger degradation when the back-gate is grounded. The back-channel of narrow fin transistors, on the other hand, needs to be inverted before degradation in the transconductance is observed. The radiation behavior of the transconductance is similar for devices with and without SEG. It is shown that the maximum variation in transconductance correlates with the mobility for narrow fin devices. This mobility varies when the transistor is rotated. For wide fin devices this correlation is not as strong.