Infinite-duration Impulse Response Filters Research Articles

Design and Implementation of a Digital Front-End With Digital Compensation for Low-Complexity 4G Radio Transceivers

A digital front-end with digital compensation is designed and implemented for low-complexity 4G radio transceivers targeted for wearable devices such as smart watches. The proposed digital front-end in the radio receiver consists of an anti-drooping filter, a decimation chain, a DC offset cancellation circuit, and an in-phase and quadrature estimation and compensation circuit whereas the digital front-end in the radio transmitter includes an anti-drooping filter, a root raised cosine filter, and an interpolation chain. The proposed DC offset cancellation circuit is based on both infinite-duration impulse response filter and moving average. The proposed in-phase and quadrature estimation and compensation circuit attains lower complexity with negligible performance loss, compared with an existing circuit. A systematic top-down strategy is taken to design and implement the proposed digital front-end from the algorithm level to the application-specific integrated circuit or ASIC hardware level. The inter-symbol interference in the transmitter and the receiver is analyzed and the unwanted emission in the transmitter is simulated as well. For all the seven bandwidths or modes in 3G and 4G, the digital front end receiver ASIC satisfies all the interference requirements, namely, in-band blocker, narrowband blocker, and adjacent channel selectivity requirements whereas the digital front end transmitter ASIC meets all the unwanted emission requirements, namely, spectrum emission mask, spurious emission, and adjacent channel leakage ratio requirements. The proposed multimode 4G digital front end receiver and transmitter ASICs exhibit a >40dB mean signal-to-noise ratio for all the seven modes and are implemented in a 180nm CMOS process technology.

A BDS Interference Suppression Technique Based on Linear Phase Adaptive IIR Notch Filters.

The continuous wave interferences (CWIs) and the narrow-band interferences (NBIs) have significantly impacted the acquisition, tracking and positioning accuracy of Beidou Navigation Satellite System (BDS) receivers. As an interference suppression technology with a simple structure and low hardware cost, the adaptive infinite-duration impulse response (IIR) notch filter has been widely employed in the receivers to mitigate the CWIs and the NBIs. However, the nonlinear phase characteristics introduced by the IIR notch filters into the navigation receivers, may cause the distortion of navigation signals. It also leads to amplitude and phase distortion of the correlation peak in acquisition and loop tracking, which consequently brings on positioning errors in the measurement domain. This problem, however, has been ignored by many previous papers. Meanwhile, some other researchers came up with the idea of equalizers and all-pass networks compensating the distortion, which is also highly infeasible. Therefore, we propose a new method of an adaptive linear phase IIR notch filter with low hardware cost which is composed of three parts—the complex IIR notch filters, the IIR linear phase structure, and the adaptive and variable step-size algorithms. Applying this method, interference suppression and the correlation peak distortion compensation can be achieved with a modest increase hardware cost. This paper compares the performance of the new method with other IIR filters in both CWI and NBI scene and presents the effects of its parameters on the anti-jamming performance. Simulation results show that the proposed module has better anti-jamming performance in NBI scene and can compensate for the correlation peak distortion in the meantime.

Exploring scalable schedules for IIR filters with resource constraints

Linear difference equations involving recurrences are fundamental equations that describe many important signal processes; in particular, infinite-duration impulse response (IIR) filters. Applying conventional dependence-preserving parallelization techniques such as software pipelining can only extract limited parallelism due to loop-carried dependences in the linear recurrences, and thus, cannot achieve scalable speedup given more resources. Furthermore, the previously published scheduling techniques did not address the tradeoffs between resource constraints and the processing speed of the resulting schedules, and thus, do not have the capability of exploring the design space of parallel schedules implementing IIR filters. In this paper, we present a novel approach, based on harmonic scheduling, that addresses the tradeoffs between resource constraints and the processing speed of the resulting schedules, which can be used to explore the design space of scalable parallel schedules implementing IIR filters with resource constraints. The salient features of our approach include a mathematical formulation of the relationship between the schedules, resource constraints and target performance, and capabilities for exploring design space in terms of those parameters. In particular, our approach can be used to successively approximate time-optimal schedules implementing IIR filters for a given target architecture. We illustrate our approach by giving an algorithm for deriving scalable schedules for IIR filters with a fixed number of identical multifunctional processors. As a further illustration, we derive rate-optimal schedules for IIR filters under more realistic constraints: using a fixed number of adders and multipliers and assuming that multiplication and addition take dissimilar execution times.