Inexact Computing Research Articles

Inexact radix-4 Booth multipliers based on new partial product generation scheme for image multiplication

Inexact computing, is a modern approach for the development of low power and high-performance digital circuits, which involves approximation stages to get the utmost accurate result and are very much applicable in some error-tolerant applications like image processing. Such applications are limited to human eyesight ability, which gives us the freedom to make the approximate output. In this manuscript, two inexact partial product generators, viz. IPPG1, IPPG2 are proposed for the design of radix-4 based 8 × 8 Booth multipliers IRBM1.1, IRBM1.2, respectively. Moreover, an inexact 4:2 compressor is also proposed to add such partial product bits generated by IPPG1 and IPPG2, and nomenclate them as IRBM2.1 and IRBM 2.2, respectively. IPPG1 and IPPG2 are designed by introducing errors in the Karnaugh’s map to reduce the circuit complexity and errors, respectively. Similarly, errors are introduced in the truth table of the exact 4:2 compressor to design a low power, high speed inexact 4:2 compressor. Error metrics estimation of such proposed inexact Booth multipliers and the state-of-the-art designs are performed using MATLAB and circuit performance parameters like area, computational delay and power dissipation are extracted using gpdk45 nm technology. While comparing, IRBM1.2 offers minimum error metrics than all other reported design so far. Moreover, in the circuit level prospect, IRBM1.1 consumes minimum power and IRBM2.2 is the fastest among its reported counter-parts. IRBM2.2 offers minimum power-delay-area (PDA) product over all of its reported counter-parts. For the validation of the proposed designs, an image multiplication, edge-detection using Sobel operator, and convolutional neural network-based application is incorporated and quality assessment parameters are measured using MATLAB.

A Design and Investigation Inexact Compressor Based on Low Power Multiplier

To achieve low power consumption and high performance, an approximate multiplier is a commonly used operation. A new approximate computation method has been used for Error Tolerant Image Processing applications. This operation is popular in error tolerance applications. Inexact computing is applied to error-tolerant digital signal processing applications where error can be tolerated. Multiplier is the basic unit of arithmetic logic unit of any computer computational unit. In this paper, a new approximate compressor computation method is proposed for error-tolerant image processing applications. An approximate compressor has been designed for better output power with an improved figure of merit. A comparison of the proposed compressor with the previous 4:2 compressor design has been investigated and a reduction in area, delay and power consumption has been achieved. A similar algorithm has been applied to 8-bit multiplier applications which have considerable error performance. With the newly designed multiplier using a compressor, the simulation results compared the best power utilization. The results of designing the multiplier indicate that the proposed design of a multiplier using an approximate compressor achieves a reduction in power by 129[Formula: see text]mw.

Design and FPGA Implementation of High Throughput and Low Latency Machine Learning based Approximate Multiplier for Image Processing Applications

One of the uses of approximate circuits is machine learning (ML) and with the help of inexact logic minimization as well as through probabilistic pruning, these approximate computing circuits can be implemented. Nowadays, these approximate circuits have been widely explored due to their essential factors such as compact silicon areas well as low power consumption in movable devices. This research work shows how a 4:2 compressor can be designed using inexact logic minimization and thereby reversing a few bits of the output to ensure efficiency as well as accuracy. The average area, propagation delay as well as the average power of the proposed 4:2 compressor is been calculated and are employed in the 8 × 8 and 16x16 Dadda multiplier and truncation and rounding-based scalable approximate multiplier (TOSAM). Using Vivado Design Software Systems in 45nm technology, all the simulations were carried out and the MATLAB tool make use of error analysis to distinguish between precise as well as approximate proposed circuits. This work is mainly concentrated on the design of exact and approximate multipliers and measures the error between them and minimization of this error using the Machine Learning approach and finally validated the results on the Artix-7 FPGA development board of part XCA7CSG324_110t, the partial products which are generated by multipliers are added using 4:2 compressor adder. In the case of digital processing at nano-metric scales, approximate or inexact computing is considered one of the important examples. For computer arithmetic designs, inexact computation plays a significant role, and the new approximate 4:2 compressors are used in a multiplier that is based on TOSAM. These architectures mainly depend on various compression aspects to enable inaccuracy in computing which is described as error rate and is also referred to as normalized error distance which is used to satisfy circuit-based figures of merit, the number of transistors, delay as well as consumption of power. For a Dadda multiplier, four distinct approaches for exploiting the suggested approximation compressors are designed as well as evaluated. The usage of approximate multipliers for image processing, as well as a wide range of simulation results, are presented in this work. When contrasted to an accurate design, the proposed designs achieve a substantial reduction in the number of transistors, power dissipation as well as delay. Furthermore, the presented multiplier models exhibit outstanding image multiplication capabilities in terms of average normalized error distance as well as peak signal-to-noise ratio that is more than 50dB for the analyzed image samples. The proposed ML-based digital system has been developed in Vivado Design Suite and synthesized which is designed using Verilog HDL. Based on obtained results, 17% reduction in power, 21% reduction in latency, and 33% improvement in throughput.

Approximate Full Adders for Energy Efficient Image Processing Applications

This paper proposes six novel approximate 1-bit full adders (AFAs) for inexact computing. The six novel AFAs namely AFA1, AFA2, AFA3, AFA4, AFA5, and AFA6 are derived from state-of-the-art exact 1-bit full adder (EFA) architectures. The performance of these AFAs is compared with reported AFAs (RAAs) in terms of design metrics (DMs) and peak-signal-to-noise-ratio (PSNR). The DMs under consideration are power, delay, power-delay-product (PDP), energy-delay-product (EDP), and area. For a fair comparison, the EFAs and proposed AFAs along with RAAs are described in Verilog, simulated, and synthesized using Cadences’ RC tool, using generic 180 nm standard cell library. The unconstrained synthesis results show that: among all the proposed AFAs, the AFA1 and AFA2 are found to be energy-efficient adders with high PSNR. The AFA1 has a total [Formula: see text][Formula: see text][Formula: see text]W, [Formula: see text][Formula: see text]ps, [Formula: see text][Formula: see text]fJ, [Formula: see text][Formula: see text]Js, [Formula: see text][Formula: see text][Formula: see text]m2, and [Formula: see text][Formula: see text]dB. And the AFA2 has the total [Formula: see text][Formula: see text][Formula: see text]W, [Formula: see text][Formula: see text]ps, [Formula: see text][Formula: see text]fJ, [Formula: see text][Formula: see text]Js, [Formula: see text][Formula: see text][Formula: see text]m2, and [Formula: see text][Formula: see text]dB.

Learning with Physical Noise or Errors

Hard learning problems have recently attracted significant attention within the cryptographic community, both as a versatile assumption on which to build various protocols, and as a potentially sound basis for lightweight (possibly side-channel and fault resistant) implementations. Yet, in this second case, a recurrent drawback of primitives based on the Learning Parity with Noise and Learning With Errors problems is their additional randomness requirements to generate noise or errors. In parallel, the move towards nanoscale devices renders modern implementations increasingly prone to various types of errors. As a result, inexact computing has emerged as a new paradigm to efficiently deal with the challenges raised by such erroneous computations, and mitigate the cost and power consumption overheads they cause. In this paper, we show that these cryptographic and electronic challenges can actually be turned into new opportunities, and provide an elegant solution one to the other. That is, we show that inexact implementations of inner product computations lead to a natural way to define new Learning with Physical Noise or Error assumptions, paving the way to more efficient and physically secure implementations, with potential interest for securing emerging Internet of Things applications.

On the Implementation of Multi-bit Inexact Adder Cells and Application towards Image De-noising

Inexact computing is an attractive concept for digital signal processing at the submicron regime. This paper proposes 2-bit inexact adder cell and further escalate to 4-bit, and 8-bit inexact adder and error metrics have been evaluated mathematically for such adder cells. The approximated design has been proposed through the simplification of the K-Maps, which leads to a substantial reduction in the propagation delay as well as energy consumption. The proposed design has been verified through the Cadence Spectre and performance parameters (such as delay, power consumption) have been evaluated through CMOS gpdk45 nm technology. Furthermore, the proposed design has been applied to image de-noising application where the performance of the images like Peak Signal to Noise Ratio (PSNR), Normalized Correlation Coefficient (NCC) and Structural Similarity Index (SSIM) has been analyzed through MATLAB, which offer the substantial improvement from its counterpart.

Low Power Multiplier using Approximate Compressor for Error Tolerant Applications

Approximate or inexact computing has gained a significant amount of attention for error tolerant systems such as signal processing and image processing applications. In this paper, a comprehensive analysis and evaluation of multipliers realized using the existing approximate 4-2 compressors towards achieving low power has been presented. 8-bit Dadda multiplier has been chosen and the power consumption comparison has been performed. The exact multiplier has also been realized to enable the calculation of power savings for the approximate multipliers. An image compression algorithm using approximate multipliers has been implemented to analyze the operability of the approximate multipliers. Accuracy of the approximate multipliers has also been computed by means of Normalized Error Distance (NED) and PSNR. All the circuits are designed using 45nm CMOS process technology and simulations are carried out using Cadence® Virtuoso design tools.

Design and Analysis of Multipliers using Radix-8 Booth Encoding Technique for Low Power and Area Consumption

As innovation scaling is arriving at its points of confinement, new methodologies have been proposed for computational efficiency. Different techniques have been proposed with advancements in technology to model high-speed along with low power consumption and smaller area multipliers. For the radix-4 booth propagation algorithm for low-power and low complexity applications, an efficient approximate 8 bit redundant multiplier is used. To minimize the complication present in modified booth encoder, approximate Booth RB encoders have been introduced by modifying the truth table with incorrect bits, which resulted in a reduction of the power delay product. Approximate computing is a relevant technique for low power and high performance circuits as used in error-tolerant applications. Approximate or inexact computing is an attractive design methodology for low power design but accomplished by loosening up the necessity of precision. It becomes critical to maintain full accuracy to attain reduced power utilization. In this paper, the design of approximate redundant binary (RB) multipliers is studied and modified to build less complex multiplier with Radix-8 modified booth encoding technique to reduce area and complexities of architectures.

Approximate Computing: A Survey of Recent Trends—Bringing Greenness to Computing and Communication

Energy-efficient computing is a much needed technological advantage for future. Approximate or inexact computing is a computing paradigm that can trade energy and computing time with accuracy of output. Recent years have seen a lot of researches in industry as well as academia. The aim of these researches is to fruitfully realize the dream of a greener and energy-efficient computing era. This paper presents a comprehensive and concise survey of the current research trends and contributions in energy-efficient computing from computational point of view. Recent developments in approximate computing hardware, software and approximate data communication have also been discussed in this article.

Design, Evaluation and Application of Approximate High-Radix Dividers

Approximate high radix dividers (HR-AXDs) are proposed and investigated in this paper. High-radix division is reviewed and inexact computing is introduced at different levels. Design parameters such as number of bits (N) and radix (r) are considered in the analysis; the replacement of exact cells with inexact cells in a binary signed-digit adder is introduced by utilizing different replacement schemes. Cell truncation and error compensation are also proposed to further extend inexact computation. Circuit-level performance and the error characteristics of the inexact high radix dividers are analyzed for the proposed designs. The combined assessment of the normal error distance, power dissipation, and delay is investigated and applications of approximate high-radix dividers are treated in detail. The simulation results show that the proposed approximate dividers offer extensive saving in terms of power dissipation, circuit complexity, and delay, while only incurring in a small degradation in accuracy thus making them possibly suitable and interesting to some applications and domains such as low power/mobile computing.

Parallel Decodable Multi-Level Unequal Burst Error Correcting Codes for Memories of Approximate Systems

Processing at the nanometric scales presents unique challenges that may require new computational paradigms such as approximate computing. In this paper a novel approach to memory protection using an unequal protection code (UEP) is proposed; this approach is in synergy with approximate (or inexact) computing. Multi-level burst error correcting UEP codes are analyzed. These codes improve over previously presented two-level burst error correcting UEP codes, because they utilize different conditions and criteria in the code partitions and decoder construction. An analysis by which multiple partitions can be selected to reduce the expected error magnitude, is provided. The area and power consumption of the parallel decoders closely depend on the desired code function. Simulation shows that the area and power consumption of the parallel error pattern generator are proportional to the partition length; the gate depth however is not strongly related to the partition length. The results of this manuscript confirm that the proposed multi-level burst error correcting UEP codes reduce the hardware overhead with no significant degradation in storage protection as potential storage application for approximate computing systems.

Guest Editorial

Guest Editorial

Design and Analysis of Inexact Floating-Point Adders

Power has become a key constraint in nanoscale integrated circuit design due to the increasing demands for mobile computing and higher integration density. As an emerging computational paradigm, an inexact circuit offers a promising approach to significantly reduce both dynamic and static power dissipation for error-tolerant applications. In this paper, an inexact floating-point adder is proposed by approximately designing an exponent subtractor and mantissa adder. Related operations such as normalization and rounding are also dealt with in terms of inexact computing. An upper bound error analysis for the average case is presented to guide the inexact design; it shows that the inexact floating-point adder design is dependent on the application data range. High dynamic range images are then processed using the proposed inexact floating-point adders to show the validity of the inexact design; comparison results show that the proposed inexact floating-point adders can improve the power consumption and power-delay product by 29.98 and 39.60 percent, respectively.

Leveraging the Error Resilience of Neural Networks for Designing Highly Energy Efficient Accelerators

In recent years, inexact computing has been increasingly regarded as one of the most promising approaches for slashing energy consumption in many applications that can tolerate a certain degree of inaccuracy. Driven by the principle of trading tolerable amounts of application accuracy in return for significant resource savings-the energy consumed, the (critical path) delay, and the (silicon) area-this approach has been limited to application-specified integrated circuits (ASICs) so far. These ASIC realizations have a narrow application scope and are often rigid in their tolerance to inaccuracy, as currently designed; the latter often determining the extent of resource savings we would achieve. In this paper, we propose to improve the application scope, error resilience and the energy savings of inexact computing by combining it with hardware neural networks. These neural networks are fast emerging as popular candidate accelerators for future heterogeneous multicore platforms and have flexible error resilience limits owing to their ability to be trained. Our results in 65-nm technology demonstrate that the proposed inexact neural network accelerator could achieve 1.78-2.67× savings in energy consumption (with corresponding delay and area savings being 1.23 and 1.46×, respectively) when compared to the existing baseline neural network implementation, at the cost of a small accuracy loss (mean squared error increases from 0.14 to 0.20 on average).

Design and Analysis of Approximate Compressors for Multiplication

Inexact (or approximate) computing is an attractive paradigm for digital processing at nanometric scales. Inexact computing is particularly interesting for computer arithmetic designs. This paper deals with the analysis and design of two new approximate 4-2 compressors for utilization in a multiplier. These designs rely on different features of compression, such that imprecision in computation (as measured by the error rate and the so-called normalized error distance) can meet with respect to circuit-based figures of merit of a design (number of transistors, delay and power consumption). Four different schemes for utilizing the proposed approximate compressors are proposed and analyzed for a Dadda multiplier. Extensive simulation results are provided and an application of the approximate multipliers to image processing is presented. The results show that the proposed designs accomplish significant reductions in power dissipation, delay and transistor count compared to an exact design; moreover, two of the proposed multiplier designs provide excellent capabilities for image multiplication with respect to average normalized error distance and peak signal-to-noise ratio (more than 50 dB for the considered image examples).

What exactly is inexact computation good for?

Our willingness to deliberately trade accuracy of computing systems for significant resource savings, notably energy consumption, got a boost from two directions. First, energy (or power, the more popularly used measure) consumption started emerging as a serious hurdle to our ability to continue scaling the complexity of processors, and thus enable ever richer computing applications. This "energy hurdle" spanned the gamut from large data-centers to portable embedded computing systems. Second, many believed that an engine of growth that supported scaling, captured by Gordon Moore's remarkable prophecy (Moore's law), was headed towards an irrevocable cliff edge - when this happens, our ability to produce computing systems whose hardware would support precise or exact computing would diminish greatly. In this talk which emphasizes the physical and hardware layers of abstraction where all of these troubles start (after all energy is rooted in thermodynamics), I will first review reasons that compelled and encouraged us to consider trading accuracy for energy savings deliberately resulting in inexact computing.

New Metrics for the Reliability of Approximate and Probabilistic Adders

Addition is a fundamental function in arithmetic operation; several adder designs have been proposed for implementations in inexact computing. These adders show different operational profiles; some of them are approximate in nature while others rely on probabilistic features of nanoscale circuits. However, there has been a lack of appropriate metrics to evaluate the efficacy of various inexact designs. In this paper, new metrics are proposed for evaluating the reliability as well as the power efficiency of approximate and probabilistic adders. Reliability is analyzed using the so-called sequential probability transition matrices (SPTMs). Error distance (ED) is initially defined as the arithmetic distance between an erroneous output and the correct output for a given input. The mean error distance (MED) and normalized error distance (NED) are then proposed as unified figures that consider the averaging effect of multiple inputs and the normalization of multiple-bit adders. It is shown that the MED is an effective metric for measuring the implementation accuracy of a multiple-bit adder and that the NED is a nearly invariant metric independent of the size of an adder. The MED is, therefore, useful in assessing the effectiveness of an approximate or probabilistic adder implementation, while the NED is useful in characterizing the reliability of a specific design. Since inexact adders are often used for saving power, the product of power and NED is further utilized for evaluating the tradeoffs between power consumption and precision. Although illustrated using adders, the proposed metrics are potentially useful in assessing other arithmetic circuit designs for applications of inexact computing.

Designing Energy-Efficient Arithmetic Operators Using Inexact Computing

It is widely acknowledged that the exponentially improving benefits of sustained technology scaling prophesied by the Moore’s Law would end within the next decade or so, attributed primarily to an understanding that switching devices can no longer function deterministically as feature sizes are scaled down to the molecular levels. The benefits of Moore’s Law could, however, continue provided systems with probabilistic or “error-prone” elements could still process information usefully. We believe that this is indeed possible in contexts where the “quality” of the results of the computation is perceptually determined by our senses—audio and video information being significant examples. To demonstrate this principle, we will show how such “inexact” computing based devices, circuits and computing architectures can be used effectively to realize many ubiquitous energy-constrained error-resilient applications. Further, we show that significant energy, performance and area gains can be achieved, while trading a perceptually tolerable level of error–that will be ultimately determined based on neurobiological models—applied in the context of video and audio data in digital signal processing. This design philosophy of inexact computing is of particular interest in the domain of embedded and (portable) multimedia applications and in application domains of budding interest such as recognition and data mining, all of which can tolerate inaccuracies to varying extents or can synthesize accurate (or sufficient) information even from inaccurate computations!

Composite matched filtering with error correction

Information theory shows that one can communicate with arbitrarily low error probability over a noisy channel. By recognizing that some types of computations can be cast as communications problems, it may be possible to compute accurately with an inexact processor. Traditional analog optical processors, for example, offer advantages of parallelism and speed but suffer from significant inaccuracies. We propose an algorithm whereby the accuracy of matched filter processors can be improved significantly at the cost of a modest increase in computational resources. Errors that are due to noisy data and/or inexact computing can be detected and in some cases corrected.