Industrial SoC Research Articles

지역경쟁력 요인이 지역경제성장에 미친 영향: 광주전남 초광역권을 중심으로

Purpose: Recently, the legal basis for the maga-region has been established, and interest in regional competitiveness is increasing. This study examines the influence of regional competitiveness factors on the growth of the regional economy, focusing on maga-regions, in terms of corporate innovation capability, economic power base, and creative potential, and examines policy implications.
 Research design, data, and methodology: This study categorizes the maga-region and uses the time series data from 2013 to 2018 to conduct a panel analysis through the LSDV (least squares dummy variable) model based on the ultra-wide area. In particular, independent variables derive competitiveness factors from the perspectives of corporate innovation capacity, economic base, and creative potential, and analyze the effects of these regional competitiveness factors on per capita GRDP and per capita GRDP growth rate.
 Results: As a result of the analysis, the influence of regional competitiveness factors based on the Gwangju and Jeonnam maga-region on GRDP per capita is as follows. First, in the field of corporate innovation capability, knowledge performance has a positive (-) effect. Next, in the economic power sector, industrial base, manufacturing base, SOC base, and financial power were found to have a statistically significant positive (+) effect. Lastly, in the creative potential sector, the talent index and amenity index had a statistically significant negative (-) was found to be affected.
 In addition, the influence of regional competitiveness factors on the per capita GRDP growth rate based on the Gwangju and Jeonnam metropolitan areas is as follows. First, in the field of corporate innovation capability, knowledge resources have a positive (+) effect. Next, in the economic power sector, the industrial base, manufacturing base, and SOC base were found to have a negative (-) effect, and the regional financial power had a positive (+) effect. Finally, in the area of creative potential, tolerance index and talent index had a positive (+) effect.
 Implications: This study has limitations in that it analyzed the influence factors of regional competitiveness factors on regional economic growth by classifying ultra-regional regions through regional dummies in a situation where interregional cooperation has not yet been established in earnest at the ultra-regional level. It is hoped that this study will serve as a starting point for monitoring regional economic growth for ultra-wide cooperation in a situation where the institutional foundation for fostering ultra-wide areas has recently been established.

The ideal industrial SOC

The ideal industrial SOC

Deterministic Synthesis of Hybrid Application-Specific Network-on-Chip Topologies

Networks-on-Chip (NoCs) enable cost-efficient and effective communication between the processing elements inside modern systems-on-chip (SoCs). NoCs with regular topologies such as meshes, tori, rings, and trees are well suited for general-purpose many core SoCs. These topologies might prove suboptimal for SoCs with predefined application characteristics and traffic patterns. Such SoCs benefit from application-specific NoC topologies, designed and optimized according to the application characteristics. This paper proposes a synthesis approach for creating hybrid, application-specific NoCs from an input floorplan and a set of use cases, describing the applications running on the SoC. The method considers latency, port count, and link length constraints. It produces hybrid topologies that utilize both NoC routers and shared buses. Furthermore, the proposed approach can insert intermediate relay routers that act as bridges or repeaters and help to reduce the cost further. Finally, the approach creates a deadlock-free routing of the communication flows by either finding deadlock-free paths or by inserting virtual channels. The benefits of the proposed method are demonstrated by comparing it to state-of-the-art approaches on a generic and an industrial SoC examples.

효율적 디버깅을 위한 디자인 체크포인트 기반 시뮬레이션 방법

디지털시스템 설계에 대한 HDL 시뮬레이션을 통한 검증 과정에서는 설계에 대한 분석 및 디버깅을 위하여 설계에 존재하는 수많은 신호선들에 대하여 시뮬레이션 실행 중에 시그널 덤핑을 통한 가시도 확보가 필요하게 된다. 그러나 이와 같은 시그널 덤핑은 일반적으로 시뮬레이션의 속도를 크게 떨어뜨리는 문제점을 가지고 있거나, 시뮬레이션의 실행 횟수를 늘리는 문제점을 초래한다. 본 논문에서는 디자인 체크포인트를 활용하여서 시그널 덤핑을 효율적이며 신속하게 수행하는 시뮬레이션 방법을 제시하고, 이를 시스템반도체급의 대규모 회로인 산업체 설계들에 적용하여 제안된 방법이 효과적임을 확인하였다. The visibility for signals in designs is required for their analysis and debug during the verification process. It could be achieved through the signal dumping for designs during the execution of HDL simulation. However, such signal dumping, in general, degrades the speed of simulation significantly, or can result in the number of simulation runs. In this paper, we have proposed an efficient and fast simulation method for dumping based on the design checkpoint, and shown its effectiveness by applying it to industrial SOC designs.

A DFT Strategy for an Industrial Communications SoC with JTAG

In this paper a system level DFT strategy with JTAG is presented to test an industrial communication and control SoC . A SoC generally integrates that microprocessor, memories, some function blocks, PLL, D/A, A/D, etc. Cores originating from different sources need different test strategies. The different test techniques are used in testing of core-based SoC system which combines scan chains, Memory-BIST and Boundary-Scan. A SoC test with JTAG architecture is implemented through a real life case (0.18µm, million gates chip). The test pin counts are reduced, test time for board test is shorter and high test coverage is achieved.

Rapid Industrial Prototyping and SoC Design of 3G/4G Wireless Systems Using an HLS Methodology

Many very-high-complexity signal processing algorithms are required in future wireless systems, giving tremendous challenges to real-time implementations. In this paper, we present our industrial r...

Rapid Industrial Prototyping and SoC Design of 3G/4G Wireless Systems Using an HLS Methodology

Many very-high-complexity signal processing algorithms are required in future wireless systems, giving tremendous challenges to real-time implementations. In this paper, we present our industrial rapid prototyping experiences on 3G/4G wireless systems using advanced signal processing algorithms in MIMO-CDMA and MIMO-OFDM systems. Core system design issues are studied and advanced receiver algorithms suitable for implementation are proposed for synchronization, MIMO equalization, and detection. We then present VLSI-oriented complexity reduction schemes and demonstrate how to interact these high-complexity algorithms with an HLS-based methodology for extensive design space exploration. This is achieved by abstracting the main effort from hard-ware iterations to the algorithmic C/C++ fixed-point design. We also analyze the advantages and limitations of the methodology. Our industrial design experience demonstrates that it is possible to enable an extensive architectural analysis in a short-time frame using HLS methodology, which significantly shortens the time to market for wireless systems.