A DFT Strategy for an Industrial Communications SoC with JTAG

Abstract

In this paper a system level DFT strategy with JTAG is presented to test an industrial communication and control SoC . A SoC generally integrates that microprocessor, memories, some function blocks, PLL, D/A, A/D, etc. Cores originating from different sources need different test strategies. The different test techniques are used in testing of core-based SoC system which combines scan chains, Memory-BIST and Boundary-Scan. A SoC test with JTAG architecture is implemented through a real life case (0.18µm, million gates chip). The test pin counts are reduced, test time for board test is shorter and high test coverage is achieved.