CMOS Inductor Research Articles

CMOS inductor design features for LTE devices

CMOS inductor design features for LTE devices

A Robust Fully-Integrated Digital-Output Inductive CMOS-MEMS Accelerometer with Improved Inductor Quality Factor

This paper presents the design, fabrication, and characterization of an inductive complementary metal oxide semiconductor micro-electromechanical systems (CMOS-MEMS) accelerometer with on-chip digital output based on LC oscillators. While most MEMS accelerometers employ capacitive detection schemes, the proposed inductive detection scheme is less susceptible to the stress-induced structural curling and deformation that are commonly seen in CMOS-MEMS devices. Oscillator-based frequency readout does not need analog to digital conversion and thus can simplify the overall system design. In this paper, a high-Q CMOS inductor was connected in series with the low-Q MEMS sensing inductor to improve its quality factor. Measurement results showed the proposed device had an offset frequency of 85.5 MHz, sensitivity of 41.6 kHz/g, noise floor of 8.2 mg/√Hz, bias instability of 0.94 kHz (11 ppm) at an average time of 2.16 s, and nonlinearity of 1.5% full-scale.

Electronic controlled CMOS inductor with patterned metal ground shields for fine inductance tuning application

This paper is on an inductance fine tuning technique which benefits from the idea of varying the number of metal plates of an inductor’s pattern ground shield (PGS) shorted to ground to change its magnetic fields. This technique is unique because the geometry and physical shape of the inductor remains untouched from its form in the process design kit (PDK) while the inductance is being tuned. The number of metal shields shorted to ground was controlled by an electronic circuit which consists of analog-to-digital converters and active switches. Both Sonnet EM simulator and Cadence Virtuoso were used for the inductor and circuit simulations. From the simulation, it was found that the inductance increased while the Q-factor decreased as more metal shields were shorted to ground. For instance, at 1.6 GHz, the simulated inductance was 8.8 nH when all metals were floated and 9.4 nH when all metals were shorted to ground. On the other hand, the simulated Q-factor was 10.4 when all metals were floated and 9.8 when all metals were shorted to ground. From both simulation and measured results, both inductance and inductance tuning range increased with frequency. From the measured results too, the inductance observed was 9.4 nH at 1.6 GHz, 10.8 nH at 2 GHz, and 13.5 nH at 2.5 GHz when all the metal shields were shorted to ground. The inductance tuning range was 6.2% at 1.6 GHz, 12.5% at 2 GHz, and 20% at 2.5 GHz. The measured results showed good correlation with the simulated results trend, but with smaller value of inductance, inductance tuning range and Q-factor.

Design Equations for Spiral and Scalable Cross Inductors on 0.35 μm CMOS Technology

This paper presents a set of design equations for spiral and new scalable cross inductors in CMOS 0.35 μm technology, relating electrical parameters of the inductor’s equivalent circuit as functions of its geometric dimensions. The procedure used to derive the design equations is described and involves electromagnetic simulation of inductors with different geometric dimensions, extraction of values for equivalent circuit model elements for each inductor and the use of multivariate regression analysis applied to generalized linear models (GLM) based on design of experiments (DoE). A p-type nine elements equivalent electrical circuit was used for the inductors, where all elements values are constants, allowing simulation on SPICE-like softwares. Results from the models obtained for both spiral and scalable cross inductors presented close match to the simulated results.

Enhancement of 5 GHz on-chip bandpass filter performance by using CMOS-MEMS inductors

We propose the use of microelectromechanical system (MEMS) inductors to enhance the performance of a 5-GHz on-chip bandpass filter. The proposed filter is implemented using the TSMC 0.18 μm one-poly six-metal (1P6M) CMOS process. For reducing substrate loss to improve filter performance, the silicon substrate underlying the filter’s MEMS inductors is removed using the Chip Implementation Center micromachining postprocess. Compared to conventional on-chip CMOS inductors on-silicon substrate, the simulation results obtained using the CMOS-MEMS inductors showed a quality factor improvement of 264.3% at 5.5 GHz. The measured insertion loss of the proposed filter with the CMOS-MEMS inductors is 3.2 dB at 4.7 GHz, and the ripple is 0.6 dB in the passband. The − 3-dB bandwidth ranges from 4.2 to 5.8 GHz. The attenuation is better than − 22 dB for frequencies ranging from 1 to 3.8 GHz and − 25 dB from 6.9 to 10 GHz in the stopband. The shape factor of the filter is 1.97:1 at an attenuation of 25/3 dB. The chip area is very small, and the optimal chip size is 1.3 × 0.75 mm2. The proposed filter could be integrated directly with the silicon base process, namely, CMOS and BiCMOS, for 5-GHz band wireless front-end applications.

High Resistivity SOI RF CMOS 인덕터의 주파수 종속 Quality Factor 모델링

High Resistivity SOI RF CMOS 인덕터의 주파수 종속 Quality Factor 모델링

Switched Substrate-Shield-Based Low-Loss CMOS Inductors for Wide Tuning Range VCOs

A switched substrate-shield inductor (SSI) topology in bulk CMOS is proposed which minimizes parasitic capacitance and substrate losses, while tuned magnetically induced currents facilitate inductor tunability. The high frequency behavior of the induced current is analyzed, resulting in intuitive insights and design guidelines for a high-performance SSI. An SSI prototype in 65-nm bulk CMOS achieves 34% inductance tunability with a quality factor of >10.3. A voltage-controlled oscillator (VCO) using SSI achieves 40.3% tuning range, from 21 to 31.6 GHz, and a phase noise of −119.1 ± 3.7 dBc/Hz at 10-MHz offset frequencies. The VCO core consumes 4.3 ± 0.2 mW from a 1-V supply.

Quality factor enhancement of an on-chip inductor through the slot-trace method

This study investigated a slot-trace method to enhance the quality factor of an on-chip inductor. To verify the effect of a slot-trace method with lowered trace loss, and to compare it with a method lowering the substrate loss, three on-chip inductors were implemented with a 0.35 μm COMS–MEMS process: a CMOS inductor, a COMS–MEMS inductor, and a COMS–MEMS inductor with a slot trace. The results show that the substrate loss mainly lowers the quality factor performance at frequencies above 2 GHz. Unlike substrate loss, trace loss influences the quality factor from low to high frequencies, and the trace loss should not be ignored. Moreover, the results show that the slot-trace method can improve the quality factor, making it useful in on-chip inductor design for the circuits of wireless communication system applications.

Performance analysis of meander-type inductor in silicon and flexible technology

In this paper meander-type inductors are designed and fabricated in silicon and flexible technology in order to investigate the performance of this topology and the possibilities of its utilization in RF applications. The CMOS inductor occupies the area of 0.104mm2, whereas the area of the inkjet printed one on flexible substrate is 1693.44mm2. In the CMOS case, the inductance is 2.8nH up to 7GHz, Q-factor is 3.9 at 8.42GHz and the resonant frequency is at 20.04GHz. The measured and simulated (ADS Momentum) results differ by as low as 7%. The flexible technology inductor yields inductance of 720nH up to 30MHz, Q-factor of 2.1 at 50MHz, while the resonant frequency is at 92MHz. The design of both components is presented in detail and obtained results are thoroughly discussed in this paper, showing that the meander topology implemented in either of these cutting edge technologies enables wideband inductor operation.

21.5-to-33.4 GHz Voltage-Controlled Oscillator Using NMOS Switched Inductors in CMOS

To demonstrate the applicability of NMOS switched variable inductors in the millimeter wave frequencies, a 21.5 to 33.4 GHz wide tuning range LC voltage-controlled oscillator (LC-VCO) with frequency tunable output buffers that uses variable inductors is reported. The measured phase noise at 10 MHz offset of VCO fabricated in a 65 nm bulk CMOS process varies from -117 to -109 dBc/Hz. The oscillator core consumes 4 or 6 mA from a 1.2 V power supply. These correspond to a record 43.3% tuning range. FOMT ranges from -191.7 to -181.9 dBc/Hz. With tunable output buffers, the measured signal output power is above -15 dBm across the entire frequencies.

A 5‐GHz Band Low‐Phase Noise CMOS VCO Using Above‐IC Technologies

ABSTRACTThis article presents a 5‐GHz band low phase noise CMOS voltage controlled oscillator (VCO) based on a high quality factor above‐IC inductor that is stacked on the top of a 0.18‐μm RF CMOS process using wafer level package technology. The measured phase noise of the VCO is −119.8 dBc/Hz at 1 MHz offset frequency, which is an improvement of 6 dB compared to a conventional VCO with on‐chip CMOS inductor. The design challenge of the grounding of the above‐IC inductor stacked on the CMOS structure is investigated in this work. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:2051–2055, 2013

High-Frequency Modeling of Poly-Si Thin-Film Transistors for Low-Cost RF Applications

In this paper, we present high-frequency characteristics of transistors and inductors in low-temperature polycrystalline-silicon thin-film transistor (LTPS TFT) technology for low-cost radio frequency applications. From 2-D device simulations, we show that the linearity of LTPS TFTs is independent of the channel length due to the presence of grain boundaries. Furthermore, since LTPS TFTs can be fabricated on insulating substrates, on-chip spiral inductors on such substrates have negligible substrate loss, leading to high quality ( <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$Q$</tex></formula> ) factor. From electromagnetic simulations, we observe that spiral inductors in LTPS TFT technology show lower parasitics, higher <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$Q$</tex> </formula> factor, and higher self-resonance frequency <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$(f_{\rm RES})$</tex> </formula> compared to typical bulk CMOS inductors having similar inductance. Such high <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$Q$</tex></formula> of inductors allows compensating for low <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$g_{m}$</tex></formula> of LTPS TFTs.

Design of magnetic RF inductor in CMOS

Traditional planar inductors in Radio Frequency (RF) Integrated Circuits (ICs) are plagued by large areas, low quality, and low frequencies. This paper describes a magnetic-based CMOS-compatible RF inductor. Magnetic-core inductors with various ferrite-filled structures, spiral structures, and magnetic material permeabilities were simulated to show that this inductor greatly improves the inductance by up to 97% and quality factor by 18.6% over a multi-GHz frequency range. The results indicate that the inductor is a very promising and viable solution to realize miniature, high quality, and high frequency on-chip inductors for high-end RF ICs.

The Integration of the Ferromagnetic Inductors into the Standard CMOS Chip

ABSTRACTAn inductor in standard CMOS process having an inductance of 52 nH and a quality factor of 1.5 at frequency equal to 80 Mhz was fabricated. The polymer passivation layer of the standard CMOS inductor was etched out. The silicon substrate under the inductor, having a thickness of 280 μm was also etched out by deep reactive ion etching (DRIE). Ferrite material ZnFe2O4 and amorphous material Fe4.7Co70.3Si15B10 was then sputtered on top of the inductor sequentially. The same sputtering procedure was also performed into the bottom of the inductor. The result is an inductor that is sandwiched by multiple ferromagnetic layers. The inductance of the new ferromagnetic inductor has increased by 15% from 52 nH to 60 nH. The quality factor has also increased by 20% from 1.5 to 1.8.

FREQUENCY RESPONSE COMPARISON OF TWO COMMON ACTIVE INDUCTORS

The frequency responses of two widely used active inductor topologies are analyzed and compared using a generalized circuit model for the active devices in the circuits. A very wideband active inductor in CMOS was subsequently fabricated and tested and the inductor exhibits a measured self-resonant frequency of 9.7 GHz.

CMOS compatible electrochemical process for improving quality factor of spiral microinductors

This study presents a post-CMOS electrochemical technique to improve the quality factor of standard CMOS inductors. This technique is a maskless process based on Silox Vapox III which possesses great etching selectivity between aluminium and SiO2 during electrochemical process. A porous silicon layer was generated on silicon substrate using this technique to increase the effective substrate resistance and to reduce the substrate loss. The result of the experiment showed that quality factor of a 1.5- and a 3.5-turn microinductor has been increased by 72.2 and 47%, respectively. A lumped-element model was used to analyse the effect of the presented technique. This technique provides a low-cost and effective process to modify CMOS components.

De-embedding method for on-wafer RF CMOS inductor measurements

In this work, an accurate de-embedding method for on-wafer RF measurements of CMOS large area devices like the inductors is presented. The method uses distributed and lumped-element models to represent the parasitic elements. The interconnect parasitics are calculated using the transmission line theory. The proposed method is compared to existing de-embedding methods. The validity of the method is checked with the DC resistance value of the interconnects as calculated from the layout and as extracted from measurements, as well as with inductance results of the fabricated inductor, extracted from measurements and from electromagnetic simulations. On-wafer S-parameter measurements have been taken from a test chip up to 20GHz.

A 5.8-GHz VCO with CMOS-compatible MEMS inductors

This paper describes a low power, low phase noise 5.8 GHz voltage controlled oscillator (VCO) with on-chip CMOS MEMS inductor. The inductor was fabricated by TSMC 0.18 μm one-poly six-metal (1P6M) CMOS process and also Chip Implementation Center (CIC) micromachining post-process. During the post-process, the dry etching was utilized to remove the oxide between the winding metals and the silicon substrate under the inductor. Due to the alleviation of parasitic capacitance and lossy substrate, the quality factor and resonant frequency will be improved and extended. In this work, quality factor up to 15 was obtained for a 1.88 nH micromachined inductor at 8.5 GHz, and the improvement is up to 88% in maximum quality factor. The CMOS and micromachined inductor were both implemented with a 5.8 GHz VCO. Compared side by side with the CMOS inductor, the CMOS MEMS inductor produced a 5 dB lower phase noise improvement at 1 MHz offset in this 5.8 GHz VCO.

Methods for Reducing Power Loss in On-Wafer Inductors

The easist way to improve the quality and decrease the size of the passive components is to improve their layout. On-wafer CMOS inductors with different patterned ground shields (PGS) and different layouts of metal coils aimed at reducing component power losses are presented in this work. Narrow extra wires at the edges of spirals and continuous via arrays in the spirals have been found to be effective. Moreover, the small n-well areas in the middle of a component and small polysilicon parts beside the coils do not harm the operation of the inductor. These results provide motivation for processing passive components stacked on top of each other.

RF CMOS inductor shielded by a high-impedance surface

We propose a high-performance inductor based on the concept of a high-impedance surface (or artificial magnetic conductor). The inductor is shielded from the silicon substrate by a high-impedance surface consisting of a lumped capacitor and inductor. Theoretical calculations comparing the proposed inductor with a conventional inductor shielded by an ordinary metal surface show that the resonant frequency and quality factor (Q) in the millimeter-wave region are higher for the proposed inductor.