Induced Interface State Generation Research Articles

Mechanism and lifetime prediction method for hot-carrier-induced degradation in lateral diffused metal-oxide-semiconductor transistors

The mechanism of hot-carrier-induced degradation in n-type lateral diffused metal-oxide-semiconductor (LDMOS) transistors is investigated. Experimental data reveal that hot-electron injection induced interface state generation in channel region is the main degradation mechanism. Since gate current (Ig) consists mainly of electron injection, Ig correlates well with device degradation. As a result, a lifetime prediction method based on Ig is presented for the purpose of projecting hot-carrier lifetime in LDMOS transistors.

Comparitive behavior of radiation and thermally generated protons in amorphous SiO2

Measurements of the transport of thermally and radiation generated protons in amorphous SiO2 gate dielectrics of metal–oxide–semiconductor field effect transistors are compared. I conclude that there is no significant behavioral difference between the two types of protons other than the fact that radiation generated protons transport more dispersively—this may be related to the proton densities involved which are typically more than 50 times smaller. From the inversion channel carrier mobility and subthreshold slope measurements on devices with thermally generated protons I conclude that the interfaces are essentially unpassivated. This observation explains why no proton induced interface state generation is observed in the case of devices containing thermally generated protons.

Electrical properties of composite gate oxides formed by rapid thermal processing

In this study, oxide stacks formed by combinations of rapid thermal chemical vapor deposition and rapid thermal oxidation have been investigated as gate dielectrics. This was achieved by performing various types of in situ rapid thermal oxidations both prior to and after oxide deposition to form composite stacked structures. The oxidation ambient and temperature was varied to study the effect on electrical properties such as mobility, leakage current, charge trapping, breakdown and hot carrier degradation. It was found that pre-oxidation prior to depositing an oxide results in a composite structure that greatly reduces the defect density by mismatching pores and weak spots in each film. The mobility behavior of these films was also found to be improved over as-deposited oxides. Post-deposition oxidation in O/sub 2/ and N/sub 2/O was also found to improve the mobility characteristics. Additionally, post-annealing in N/sub 2/O was effective in improving the reliability of deposited oxides. These N/sub 2/O annealed films had low interface trap densities, improved high field mobility, very low charge trapping characteristics and enhanced resistance to hot carrier induced interface state generation. These improvements are attributed to 1) the presence of nitrogen at the interface and 2) to the reduction of nitrogen and hydrogen concentrations in the bulk of the oxide. The role of atomic oxygen during the post-anneal in N/sub 2/O is discussed along with differences in annealing ambients.

Time dependent hot-carrier induced interface state generation in deep submicron LDD nMOSFETs

The physical mechanism for stress time dependence of hot-carrier induced interface state generation has been investigated by using the lucky-electron model based rate equation and the charge-pumping technique. Both the effective value of critical energy for interface state generation and the potential barrier for channel hot-electron injection into the gate electrode have been evaluated. The time dependence of interface state generation was formulated with combination of the simple degradation model and the measured barrier heights. It was concluded that the major physical mechanism for self-limiting behavior is the decrement of injected hot-carriers into the oxide due to enhancement of energy-barrier caused by the negative charge build-up at the SiSiO 2 interface.

Hot hole induced interface state generation and annihilation in SOI MOSFETs

The effects of pure hot hole injection in SOI MOSFET's are investigated. Pure hot hole injection is achieved by exploiting the opposite channel based carrier injection phenomenon. It is found that significant amounts of interface states are generated, some of which are annihilated by a subsequent hot electron injection pulse. A power law of the form D/sub it/(t)=Kt/sup n/ with n close to 0.25 was obtained, indicating a more complex, diffusion limited, electrochemical reaction at the interface than previously reported.

Effect of Growth Conditions on the Reliability of Ultrathin MOS Gate Oxides

AbstractIn this work we demonstrate that in MOS devices the reliability of ultrathin (< 100Å) gate oxide is a strong function of growth conditions, such as, temperature and the growth rate. In addition, for constant current gate injection the degradation of SiO2 is enhanced as the thickness is reduced. We attribute this to physical stress in SiO2 resulting from the growth process. The degradation is always more for those growth conditions which result in higher physical stress in SiO2. Higher temperatures and slower oxidation rates allow stress relaxation through viscous flow and hence result in SiO2 of better reliability. We also found that for constant current stressing, the interface damage is more at the collecting electrode than at the injecting electrode. ΔDit (stress induced interface state generation) can be reduced after a high temperature Ar post anneal after the gate oxide growth.

Characteristics of sub-1/4-μm gate surface channel PMOSFET's using a multilayer gate structure of boron-doped poly-Si on thin nitrogen-doped poly-Si

This paper reports the effects of a new p/sup +/ gate structure (MBN gate) on the properties of surface channel PMOSFET's with an extremely thin gate oxide. The MBN gate is a multilayer gate structure of boron-doped poly Si on thin nitrogen-doped poly-Si. The thin nitrogen-doped Si layer effectively suppresses boron diffusion, so that the gate poly Si can be doped with boron in high concentration without the fear of boron penetration. Gate depletion effects are well suppressed. Effective hole mobility is improved due to the reduction of the initial interface state density. The hot-hole induced interface state generation is shown to be the dominant clause of degradation in the 1/4-/spl mu/m level PMOSFET's, and less Gm degradation is found in the MBN-gate PMOSFET's than in conventional p/sup +/-gate PMOSFET's. Finally, with respect to the reliability of the gate oxide, a conventional p/sup +/ gate with boron penetration exhibits an increase in short-time defect related breakdown during constant-current FN stressing. Short-time defect-related breakdown is not observed in the MBN gate but a slight decrease in charge to breakdown. >

Effects of hot carrier induced interface state generation in submicron LDD MOSFET's

A two-dimensional numerical simulation including a new interface state generation model has been developed to study the performance variation of a LDD MOSFET after a dc voltage stress. The spatial distribution of hot carrier induced interface states is calculated with a breaking silicon-hydrogen bond model. Mobility degradation and reduction of conduction charge due to interface traps are considered. A 0.6 /spl mu/m LDD MOSFET was fabricated. The drain current degradation and the substrate current variation after a stress were characterized to compare the simulation. A reduction of the substrate current at V/sub g//spl sime/0.5 V/sub d/ in a stressed device was observed from both the measurement and the simulation. Our study reveals that the reduction is attributed to a distance between a maximum channel electric field and generated interface states.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Generation of interface states at the silicon/oxide interface due to hot-electron injection

By considering the decomposition of water-related bonds at the silicon/oxide interfaces, theoretical expressions for the hot-electron induced interface state generation and threshold-voltage shift are developed. Results demonstrate that the relation between the threshold-voltage shift and the hot-electron fluence needs not follow the power law. The developed expression of the threshold-voltage shift is a function of the initial interface trap density, interface hardness, density of water-related chemical bond, and the capture cross section of interface trap and can be used to explain most of the reported experiments. When the trapping rate and the generation rate are close to each other, a power law dependence of the threshold-voltage shift will be observed in a wide range of injection fluence. However, if the trapping rate is greater than the generation rate or for a sample with large hardness and small initial trap density, a quasi-saturation region is observed because of most of the interface trap being filled and the small amount of generated traps. Saturation of the threshold-voltage shift will occur when most of the water-related bonds are dissociated and the created traps are filled.

Radiation induced interface states and ESR evidence for room temperature interactions between molecular hydrogen and silicon dangling bonds in amorphous SiO 2 Films on Si

We establish strong experimental evidence linking reactions between molecular hydrogen and E' center hole traps to the radiation induced interface state generation process in metal/oxide/silicon (MOS) devices.

Radiation and high field induced interface state generation in MOS structures with modified nitrided oxide

Radiation and high field induced interface state generation in MOS structures with modified nitrided oxide

Study of interface state generation in thin oxynitride gate dielectrics under hot-electron stressing

The hot-electron-induced interface state generation in thin (˜8.6nm) oxynitride films prepared by rapid thermal reoxidation (RTO) of rapidly thermal nitrided (RTN) SiO2 have been studied. Both MOS capacitors and MOSFETs were used as testing devices. For MOSFETs, charge-pumping current Icp measurement was performed to monitor the increase ΔDit of interface state density. It is found that the optimised RTN and RTO processes could produce devices with a significantly improved resistance against the hotelectron- induced interface state generation.