Indium Gallium Zinc Oxide Channel Research Articles

The Performance Improvement of N2 Plasma Treatment on ZrO2 Gate Dielectric Thin-Film Transistors with Atmospheric Pressure Plasma-Enhanced Chemical Vapor Deposition IGZO Channel.

The aim of this paper is to illustrate the N2 plasma treatment for high-κ ZrO2 gate dielectric stack (30 nm) with indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs). Experimental results reveal that a suitable incorporation of nitrogen atoms could enhance the device performance by eliminating the oxygen vacancies and provide an amorphous surface with better surface roughness. With N2 plasma treated ZrO2 gate, IGZO channel is fabricated by atmospheric pressure plasma-enhanced chemical vapor deposition (AP-PECVD) technique. The best performance of the AP-PECVD IGZO TFTs are obtained with 20 W-90 sec N2 plasma treatment with field-effect mobility (μ(FET)) of 22.5 cm2/V-s, subthreshold swing (SS) of 155 mV/dec, and on/off current ratio (I(on)/I(off)) of 1.49 x 10(7).

InGaZnO Thin-Film Transistors With Coplanar Control Gates for Single-Device Logic Applications

Neuron thin-film transistors (TFTs) with coplanar control gates based on RF sputtering-deposited amorphous indium–gallium–zinc oxide (IGZO) layer are fabricated. Two coplanar control gates, capacitively coupled with the floating gate, can effectively control the neutron TFT. The drain current of the TFT can be controlled by the logic states (and the voltage magnitude) of the control gates, which is attributed to the modulation of an electron accumulation region in the IGZO channel layer. The neuron TFT can produce three output states, which could be used to implement an abacuslike counting scheme. It can also be used to implement the OR and AND logic functions on the same device.

Flexible nonvolatile memory transistors using indium gallium zinc oxide-channel and ferroelectric polymer poly(vinylidene fluoride-co-trifluoroethylene) fabricated on elastomer substrate

The authors demonstrated flexible memory thin-film transistors (MTFTs) with organic ferroelectric polymer poly(vinylidene fluoride-co-trifluoroethylene) and an amorphous oxide semiconducting indium gallium zinc oxide channel on the elastomer substrates. The carrier mobility, memory on/off ratio, and subthreshold swing of the flexible MTFTs showed 21 cm2V−1s−1, 107, and 0.5–1 V/decade, respectively. The memory window of 13 V at ±20 V programming was confirmed for the device without any interface layer. These obtained values did not significantly change when the substrate was bent with a radius of curvature of 10 mm. The memory on/off ratio was initially 5 × 104 and maintained at 102 even after a lapse of 3600 s. The fabricated MTFTs exhibited encouraging characteristics on the elastomer that are sufficient to realize mechanically flexible nonvolatile memory devices.

Energy-Efficient Artificial Synapses Based on Flexible IGZO Electric-Double-Layer Transistors

Flexible low-voltage indium-gallium-zinc-oxide (IGZO) electric-double-layer transistors are fabricated on polyethylene terephthalate substrates at room temperature and proposed for energy-efficient artificial synapse application. The IGZO channel conductance and the gate voltage pulse are regarded as synaptic weight and synaptic spike, respectively. The energy consumption of our IGZO synaptic transistor is estimated to be as low as $\sim 0.23$ pJ/spike. Short-term synaptic plasticity and high-pass filtering behaviors are also mimicked in an individual IGZO synaptic transistor.

High stability mechanisms of quinary indium gallium zinc aluminum oxide multicomponent oxide films and thin film transistors

Quinary indium gallium zinc aluminum oxide (IGZAO) multicomponent oxide films were deposited using indium gallium zinc oxide (IGZO) target and Al target by radio frequency magnetron cosputtering system. An extra carrier transport pathway could be provided by the 3 s orbitals of Al cations to improve the electrical properties of the IGZO films, and the oxygen instability could be stabilized by the strong Al-O bonds in the IGZAO films. The electron concentration change and the electron mobility change of the IGZAO films for aging time of 10 days under an air environment at 40 °C and 75% humidity were 20.1% and 2.4%, respectively. The experimental results verified the performance stability of the IGZAO films. Compared with the thin film transistors (TFTs) using conventional IGZO channel layer, in conducting the stability of TFTs with IGZAO channel layer, the transconductance gm change, threshold voltage VT change, and the subthreshold swing S value change under the same aging condition were improved to 7.9%, 10.5%, and 14.8%, respectively. Furthermore, the stable performances of the IGZAO TFTs were also verified by the positive gate bias stress. In this research, the quinary IGZAO multicomponent oxide films and that applied in TFTs were the first studied in the literature.

Hysteresis and threshold switching characteristics in thin-film-transistors with inserted Pt-Fe2O3 core–shell nanocrystals

Hysteresis and threshold switching characteristics were investigated in the indium-gallium-zinc-oxide (IGZO) thin-film-transistors (TFTs) with inserted Pt-Fe2O3 core–shell nanocrystals (NCs) layer between source/drain and IGZO channel. The output curves showed the hysteresis with threshold drain voltage and the transfer curves showed the hysteresis with the shift of threshold gate voltage. These hysteresis, threshold switching, and shift of threshold voltage in both output and transfer curves are caused by charging of inserted NCs. These unique features demonstrated the memory and on/off switching operation by controlling both threshold gate and drain voltages through charging NCs.

100-nm IGZO Thin-Film Transistors With Film Profile Engineering

100-nm indium-gallium-zinc-oxide (IGZO) thin-film transistors were fabricated with a one-mask process, which takes the advantage of photoresist trimming technique and the concept of film profile engineering (FPE). With I-line-based photolithography, a device with channel length of 97 nm has been successfully fabricated. The FPE device contains a conformal Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> gate oxide, concave IGZO channel, and discrete source/drain (S/D) Al contacts. Good device characteristics including a high-ON/OFF current ratio (>10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> ) and good subthreshold swing (140 mV/decade) are obtained. Nonetheless, high-S/D series resistance presents a key issue that needs to be addressed for further device performance improvement.

Flexible AMOLEDs with low‐temperature‐processed TFT backplane technologies

AbstractDevelopments of backplane technologies, which are one of the challenging topics, toward the realization of flexible active matrix organic light‐emitting diodes (AMOLEDs) are discussed in this paper. Plastic substrates including polyimide are considered as a good candidate for substrates of flexible AMOLEDs. The fabrication process flows based on plastic substrates are explained. Limited by the temperature that plastic substrates can sustain, TFT technologies with maximum processing temperature below 400 °C must be developed. Considering the stringent requirements of AMOLEDs, both oxide thin‐film transistors (TFTs) and ultra‐low‐temperature poly‐silicon TFTs (U‐LTPS TFTs) are investigated. First, oxide TFTs with representative indium gallium zinc oxide channel layer are fabricated on polyimide substrates. The threshold voltage shifts under bias stress and under bending test are small. Thus, a 4.0‐in. flexible AMOLED is demonstrated with indium gallium zinc oxide TFTs, showing good panel performance and flexibility. Further, the oxide TFTs based on indium tin zinc oxide channel layer with high mobility and good stability are discussed. The mobility can be higher than 20 cm2/Vs, and threshold voltage shifts under both voltage stress and current stress are almost negligible, proving the potential of oxide TFT technology. On the other hand, the U‐LTPS TFTs are also developed. It is confirmed that dehydrogenation and dopant activation can be effectively performed at a temperature within 400 °C. The performance of U‐LTPS TFTs on polyimide is compatible to those of TFTs on glass. Also, the performance of devices on polyimide can be kept intact after devices de‐bonded from glass carrier. Finally, a 4.3‐in. flexible AMOLED is also demonstrated with U‐LTPS TFTs.

Highly Reliable Multiple-Channel IGZO Thin-Film Transistors Employing Asymmetric Spacing and Channel Width

We designed and fabricated highly reliable multiple-channel indium-gallium-zinc oxide (IGZO) thin-film transistors (TFTs) without any additional fabrication processes. We also investigated the geometric factors of the multiple-channel structure that influence the reliability of the IGZO TFTs in high saturation mode, such as the spacing and width of the subchannels. The proposed device exhibited superior reliability(Δ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> <; 0.2 V) due to the larger spacing in the central part of the IGZO channel region, whereas the TFTs with the conventional structure showed a 3 V Δ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> shift. This is due to the more effective emission of heat induced inside the TFTs duringoperation.

Thermal stability of metal Ohmic contacts in indium gallium zinc oxide transistors using a graphene barrier layer

The excellent impermeability of graphene was exploited to produce stable ohmic contact at the interface between Al metal and a semiconducting indium gallium zinc oxide (IGZO) layer after high-temperature annealing. Thin film transistors (TFTs) were fabricated with and without a graphene interlayer between the Al metal and the IGZO channel region. Metal contact at the interface prepared without a graphene interlayer showed serious instabilities in the IGZO TFT under thermal annealing; however, the insertion of a graphene interlayer between the IGZO channel and the Al metal offered good stability under repeated high-temperature annealing cycles and maintained ohmic contact.

Non-volatile nano-floating gate memory with Pt-Fe2O3 composite nanoparticles and indium gallium zinc oxide channel

Non-volatile nano-floating gate memory characteristics with colloidal Pt-Fe2O3 composite nanoparticles with a mostly core–shell structure and indium gallium zinc oxide channel layer were investigated. The Pt-Fe2O3 nanoparticles were chemically synthesized through the preferential oxidation of Fe and subsequent pileup of Pt into the core in the colloidal solution. The uniformly assembled nanoparticles’ layer could be formed with a density of ~3 × 1011 cm−2 by a solution-based dip-coating process. The Pt core (~3 nm in diameter) and Fe2O3-shell (~6 nm in thickness) played the roles of the charge storage node and tunneling barrier, respectively. The device exhibited the hysteresis in current–voltage measurement with a threshold voltage shift of ~4.76 V by gate voltage sweeping to +30 V. It also showed the threshold shift of ~0.66 V after pulse programming at +20 V for 1 s with retention > ~65 % after 104 s. These results demonstrate the feasibility of using colloidal nanoparticles with core–shell structure as gate stacks of the charge storage node and tunneling dielectric for low-temperature and solution-based processed non-volatile memory devices.

Electrical Properties of the Thin-Film Transistor With an Indium–Gallium–Zinc Oxide Channel and an Aluminium Oxide Gate Dielectric Stack Formed by Solution-Based Atmospheric Pressure Deposition

We developed a thin-film transistor (TFT) with an amorphous-indium–gallium–zinc oxide (IGZO) channel and aluminium oxide ( <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\hbox{AlO}_{\rm x}$</tex></formula> ) gate dielectric stack that was formed using a solution-based atmospheric pressure chemical vapor deposition. A breakdown electric field of 5.9 MV/cm and a dielectric constant of 6.8 were achieved for the <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\hbox{AlO}_{\rm x}$</tex></formula> gate dielectric. The nonvacuum-processed IGZO TFT gave a field-effect mobility of 4.2 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\hbox{cm}^{2}\cdot \hbox{V}^{-1}\cdot \hbox{s}^{-1}$</tex> </formula> and an on/off current ratio of over <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\hbox{10}^{8}$</tex></formula> . Moreover, the proposed deposition method is a powerful tool for material research to explore multicomponent oxide insulators and semiconductors.

P‐14: High Performance Solution‐Processed IGZO TFTs Formed by Using a High‐Pressure Annealing Method

AbstractWe have developed a noble high‐pressure annealing (HPA) method for solution‐processed indium gallium zinc oxide (IGZO) thin‐film transistors (TFTs). As the pressure increased, the electrical properties of solution‐processed IGZO TFTs were improved. This could be attributed to the decomposition promotion of metal‐organic bonding and the density decrease of interface defect states between IGZO channel and SiO2 gate insulator. For the IGZO channel layer annealed for 3 h at 1 MPa and 300 °C, its channel mobility (μFEFE), threshold voltage (Vth), subthreshold gate swing (S.S) and on/off ratio were 1.02 cm2/Vs, 2.47 V, 0.48 V/dec. and 7.5×106, respectively.

IGZO 박막트랜지스터의 동작특성

IGZO (indium gallium zinc oxide) 박막트랜지스터는, 활성층 채널의 폭과 길이의 비가 고정된 경우에도, 채널 길이가 길어지면 게이트전압에 대한 드레인 전류의 특성곡선이 양의 전압 방향으로 이동하고 전계효과이동도는 낮아졌다. 채널의 길이와 폭이 고정된 상태에서는, 드레인이 전압 높은 경우에 전계효과이동도가 낮고 문턱아래 기울기가 큰 특성을 보였다. 이러한 현상은 IGZO 채널층의 일함수가 커서 소스/드레인 전극과 채널층의 접합부 띠굽음이 규소반도체의 경우와 반대방향으로 나타나는 것에 기인하는 것으로 해석된다. According to the increase of the channel length with fixed width/length, characteristic curves of drain current as a function of gate bias voltage of indium gallium zinc oxide (IGZO) thin-film transistors moved to a positive direction of gate voltage, and field-effect mobility decreased. In case of fixed length and width of channel, field-effect mobility was lower and subthreshold slope was larger when drain bias voltage was higher. Due to large work function of IGZO, band bending at the junction region between IGZO channel and source/drain electrodes was expected to be in opposite direction to that between silicon and metal electrodes; this could explain the above results.

Fast All-Transparent Integrated Circuits Based on Indium Gallium Zinc Oxide Thin-Film Transistors

We describe the fabrication and characterization of visible transparent small-scale indium gallium zinc oxide (IGZO) integrated circuits. The IGZO channel and indium tin oxide (ITO) contacts and interconnects were pulsed laser deposited at room temperature. Low-temperature (200 °C ) atomic-layer-deposited Al2O3 was used as the gate dielectric in bottom-gated thin-film transistors with field-effect mobility near 15 cm2/V·s. Logic inverters and ring oscillators were fabricated and characterized, with operations at frequencies as high as 2.1 MHz, corresponding to a propagation delay of less than 48 ns/stage with a supply voltage of 25 V. To the best of our knowledge, these are the fastest all-transparent oxide semiconductor circuits reported to date.

Constant-Voltage-Bias Stress Testing of a-IGZO Thin-Film Transistors

Constant-voltage-bias (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> = 30 V) stress measurements are performed for a period of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> s on thin-film transistors (TFTs) with amorphous indium-gallium-zinc-oxide (IGZO) channel layers fabricated via RF sputtering using a postdeposition annealing temperature of 200degC, 250degC, or 300degC. Thermal silicon dioxide is employed as a TFT bottom-gate insulator. All SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /IGZO TFTs tested exhibit the following: 1) a positive rigid log(I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> )- V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> transfer curve shift; 2) a continuous drain-current decrease over the entire stress duration; and 3) recovery of the log(I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> )-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> transfer curve toward the prestressed state when the stressed TFT is left unbiased in the dark at room temperature for an extended period of time. The SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /IGZO TFTs subjected to a higher postdeposition annealing temperature are more stable. A small (and typically negligible) amount of clockwise hysteresis is present in the log(I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> ) -V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> transfer curves of IGZO TFTs. These instability and hysteresis observations are consistent with a SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> / IGZO TFT instability mechanism involving electron trapping within the IGZO channel layer.

Impact of high-k TiOx dielectric on device performance of indium-gallium-zinc oxide transistors

We investigated the effect of the high-k TiOx (k∼40) gate dielectric on the mobility (μFE) of indium-gallium-zinc oxide (IGZO) transistors. As the thickness of the TiOx layer at the interface of the IGZO channel and SiNx gate dielectric layer increased from 2 to 8 nm, the μFE value was monotonously reduced from 9.9 to 1.8 cm2/V s. The degradation of the mobility was attributed to the Coulomb scattering mechanism rather than the phonon scattering mechanism of the high-k TiOx layer based on the behavior of the temperature-dependent mobilities for all of the IGZO transistors.

Bias stress stability of indium gallium zinc oxide channel based transparent thin film transistors

The effects of bias stress on transistor performance are important when considering nontraditional channel materials for thin film transistors. Applying a gate bias stress to indium gallium zinc oxide transparent thin film transistors was found to induce a parallel threshold voltage shift without changing the field effect mobility or the subthreshold gate voltage swing. The threshold voltage change is logarithmically dependent on the duration of the bias stress implying a charge tunneling mechanism resulting in trapped negative charge screening the applied gate voltage.

High performance thin film transistors with cosputtered amorphous indium gallium zinc oxide channel

The authors report the fabrication of high performance thin film transistors (TFTs) with an amorphous indium gallium zinc oxide (a-IGZO) channel, which was deposited by cosputtering using a dual IGZO and indium zinc oxide (IZO) target. The effect of the indium content on the device performance of the a-IGZO TFTs was investigated. At a relatively low IZO power of 400W, the field-effect mobility (μFE) and subthreshold gate swing (S) of the a-IGZO TFTs were dramatically improved to 19.3cm2∕Vs and 0.35V/decade, respectively, compared to those (11.2cm2∕Vs and 1.11V/decade) for the TFTs with the a-IGZO channel (reference sample) prepared using only the IGZO target. The enhancement in the subthreshold IDS-VGS characteristics at an IZO power of 400W compared to those of the reference sample was attributed to the reduction of the interface trap density rather than the reduction of the bulk defects of the a-IGZO channel.

Room temperature pulsed laser deposited indium gallium zinc oxide channel based transparent thin film transistors

Indium gallium zinc oxide deposited by pulsed laser deposition at room temperature was used as a channel layer to fabricate transparent thin film transistors with good electrical characteristics: field effect mobility of 11cm2V−1s−1 and subthreshold voltage swing of 0.20V∕decade. By varying the oxygen partial pressure during deposition the conductivity of the channel was controlled to give a low off-current of ∼10pA and a drain current on/off ratio of ∼5×107. Changing the channel layer thickness was a viable way to vary the threshold voltage. The effect of the gate dielectric on the electrical behavior was also explored.