Increasing Chip Size Research Articles

Improving Emission Uniformity of InGaN/GaN-Based Vertical LEDs by Using Reflective ITO/Ag n-Contact

We investigated the effect of Ti/Al and ITO/Ag n-type contacts on the emission uniformity and light output of different chip-size vertical-geometry light-emitting diodes (VLEDs) for vehicle headlamp application. The forward voltage of the Ti/Al-based reference VLEDs decreased from 3.38 to 3.20 V at 1500 mA with increasing chip size from (1280 × 1000 µm2) to (1700 × 1700 µm2), whereas that of the ITO/Ag-based samples changed from 3.37 to 3.15 V. Regardless of chip size, the ITO/Ag-based samples revealed higher light output power than the reference samples. For example, the ITO/Ag-based samples (chip size of 1700 × 1700 µm2) exhibited 3.4% higher light output power at 1500 mA than the reference samples. The ITO/Ag samples underwent less degradation in the Wall-plug efficiency (WPE) than the reference sample. For instance, the ITO/Ag-based samples (1700 × 1700 µm2) gave 4.8% higher WPE at 1500 mA than the reference samples. The ITO/Ag-based samples illustrated more uniform emission than the Ti/Al-based sample. Both the reference and ITO/Ag-based samples underwent no degradation when operated at 1500 mA for 1000 h.

Integrated Tool Set for Control, Calibration, and Characterization of Quantum Devices Applied to Superconducting Qubits

Efforts to scale-up quantum computation have reached a point where the principal limiting factor is not the number of qubits, but the entangling gate infidelity. However, the highly detailed system characterization required to understand the underlying error sources is an arduous process and impractical with increasing chip size. Open-loop optimal control techniques allow for the improvement of gates but are limited by the models they are based on. To rectify the situation, we provide an integrated open-source tool-set for Control, Calibration and Characterization, capable of open-loop pulse optimization, model-free calibration, model fitting and refinement. We present a methodology to combine these tools to find a quantitatively accurate system model, high-fidelity gates and an approximate error budget, all based on a high-performance, feature-rich simulator. We illustrate our methods using simulated fixed-frequency superconducting qubits for which we learn model parameters with less than 1% error and derive a coherence limited cross-resonance (CR) gate that achieves 99.6% fidelity without need for calibration.

Numerical Investigation of Light Extraction Efficiency of GaN-based Vertical Blue Micron-Scale Light-Emitting Diode Structures.

The light extraction efficiency (LEE) of GaN-based vertical blue micron-scale light-emitting diode (μ-LED) structures was investigated numerically using three-dimensional finite-difference timedomain (FDTD) methods. The entire μ-LED chip was included in the FDTD computational domain to determine the LEE accurately. As the lateral dimensions of μ-LEDs increased from 5 to 30 μm, the LEE decreased gradually because of the increased portion of light trapped inside the LED chip and the increased light absorption in the GaN layers with increasing chip size. The LEE varied strongly with the p-GaN thickness for the μ-LED with a flattop surface, which could be explained by the strong dependence of the spatial distribution of the emission patterns on the p-GaN thickness. This dependence on the p-GaN thickness decreased when the surface of the μ-LED chip was patterned. A high LEE of >80% could be achieved in LEDs with properly chosen parameters. The FDTD simulation results presented in this study are expected to be employed advantageously in designing μ-LED structures with a high LEE.

Theoretical Performance Limit of the IGBT

In this paper, an analytical model of insulated gate bipolar transistor (IGBT) on-state voltage ( ${V}_{\mathrm {{ {{ON}}}}}$ ) and turn-off loss ( ${E}_{\mathrm {{ {{OFF}}}}}$ ) is developed to find the optimum solution (minimum power loss) for a given application. With this model, it is found that IGBT on-state voltage is limited by the fact that holes can only flow from the anode to the cathode. The minimum on-state voltage for a Si IGBT with 110- $\mu \text{m}$ wide drift region is found out to be around 0.835 V at 100 A/cm2 and room temperature. For a given operating frequency and chip size, a tradeoff between on-state voltage and turn-off loss that gives minimum device power loss can be achieved by manipulating the carrier profile in the drift region with an optimum structure design. This minimum device loss decreases mildly with increasing chip size, i.e., a merely 45% loss reduction when the chip size increases from 0.2 to 5 cm2. These results clearly indicate that the performance of an IGBT is not area sensitive. They are encouraging for device manufacturers who wish to reduce the device chip size to lower cost. However, the constraint comes from the device thermal dissipation capabilities which decrease quickly with decreasing chip size. These results are validated with numerical 2-D device simulations for a large variety of device structures, chip size, and operating frequencies (2 to 200 kHz). State-of-the-art IGBT product performance is compared against the theoretical limit indicating there is still substantial room for improvement at low and high frequencies.

Design of oxide-confined and temperature stable long wavelength Vertical Cavity Surface Emitting Laser for optical interconnects

One of the important attributes of Vertical Cavity Surface Emitting Laser for applications in optical interconnects is stable high temperature performance. In addition to temperature insensitivity, power dissipation is other major concern in the field of on-chip optical interconnects. With ever increasing chip size and functionalities, researchers are aggressively looking for temperature stability and power reduction in each department. Also the future emerging system of on-chip devices require long wavelength laser for high capacity applications. This paper deals with the designing of oxide-confined VCSEL structure operating at long wavelength i.e. 1310nm. Atlas Silvaco frame work is used to design VCSEL and to analyze its electrical and thermal behavior with state of the art modules. The static properties of the proposed VCSEL are analyzed at different oxide aperture diameter and temperature. It is observed that the future obligatory performance can be attained with this proposed design of VCSEL structure model even operating at low current densities and reduced oxide-aperture diameter equal to 3μm. The average error between the simulated and analytical power conversion efficiency is less than 5%.

Deep Trench Capacitor in Three Dimensional Through Silicon via Keepout Area for Electrostatic Discharge Protection

To fully enable and leverage the power of advanced processors, products must have abundant cache memory with much shorter access paths without increasing chip size. This requires growing products in the z-direction by building stacked chips (3-D chips). To optimize 3-D product costs, the area consumed by other processing requirements such as electrostatic discharge (ESD) protection needs to be as efficient as possible. Placing ESD structures made with deep trench capacitors in 3-D through silicon via keepout areas optimizes silicon area since these structures enable placement of ESD devices in space that would otherwise not be used.

Evaluation new corner stress relief structure layout for high robust metallization

For a high robust metallization it is necessary to solve different problems related to migration mechanisms and thermo-mechanical stress in the material. Extended operating conditions and challenging assembling processes influence stress behaviour in chip corners. Typically the corner area of the chip is excluded for use. For higher stress load the forbidden area increases. But effort for demanding mission profiles of a product should not cumulative in increasing chip size. Simulation can help to a better understanding of mechanical stress in the chip corner and chip-package interaction.Corner stress relief structures lower the influence of high thermo-mechanical stress. A high functional corner stress relief structure allows a more efficient chip design. In this work of corner stress relief structure is presented and an evaluation structure is shown which allows to prove the effectiveness of the stress relief.

Reliability Investigation of Large GaAs Pixel Detectors Flip-Chip-Bonded on Si Readout Chips

Lead-free reflow soldering techniques applying AuSn as well as SnAg electroplated bumps were chosen for the evaluation of the flip-chip-bonding process for X-ray pixel detectors. Both solders can be used in pick-and-place processes with a subsequent batch reflow suitable for high-volume production. AuSn solder was selected because of its fluxless bondability, good wettability, and self-alignment process capability, and SnAg solder was chosen for its more ductile behavior and lower yield stress compared to AuSn. GaAs test chips with daisy chain and four-point Kelvin probe structures together with appropriate Si test substrates were designed, manufactured, and bumped. Test chips with 55 and 170 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu{\rm m}$</tex></formula> pitch and different chip sizes (maximum 16.3 down to 4 mm square) were used. AuSn bumps were deposited by electroplating (first Au and a thin Sn layer on top). Thick Au bonding pads were formed on substrate side in case of AuSn bumps. Two under-bump metallizations (UBMs) were used for the SnAg samples: Cu and Ni. Finite element (FE) simulation was performed comparing AuSn and SnAg interconnections and different chip sizes. A local model was designed for bump interconnection and a global octant model for the assembly process. Very high values were calculated for the peel stress using AuSn bumps. SnAg bumps, on the other hand, showed 3–5 times reduction in peel stress depending on the chip size. A flip-chip-bonding process setup was carried out for both solder types (AuSn as well as SnAg), with an analysis of the samples by electrical measurements, cross-sectioning, and scanning electron microscopy. Due to the different coefficients of the thermal expansion of GaAs and Si, no stable bonding process was obtained for the AuSn modules as already predicted by the FE simulation. With increasing chip size, failures like pad lift or cracking of the GaAs bulk material were observed. In comparison, the SnAg samples showed good bonding results. This technology was then selected to assemble test modules for thermal cycling between <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${-}{55}$</tex></formula> and <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${+}{\rm 125}^{\circ}{\rm C}$</tex></formula> comparing Cu and Ni as UBM. The modules were qualified by electrical monitoring as well as cross sectioning. More than 200 cycles were reached by the 55- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu{\rm m}$</tex></formula> pitch 16.3-mm square bonded GaAs chips and about 400 by the smallest 4-mm square chips, although no underfilling was used. The dominant failure mode was fracture within the solder. Based on experimental and simulation results, functional 256 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\,\times\,$</tex></formula> 256 GaAs pixel detectors with a chip size of 14 mm <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\,\times\,$</tex></formula> 14 mm were assembled on Si readout chips using SnAg bumps on a Cu UBM. Finally, these X-ray image sensors were wire-bonded to a printed circuit board and successfully tested, showing an yield (at the pixel level) of about 98%.

Quo Vadis Nanoelectronics?

AbstractSemiconductor devices continue to be downscaled on a regular basis as technology provides the ability to make smaller dimensions via improved lithography, a process which is known as Moore's Law. However, the driving force for the continued increase in number of devices on a chip is not this reduction in size, but the ability to put more functions on a chip with the same cost per unit area of Si. Nevertheless, it is not clear that our technology for Si devices can continue to work much longer. Here, I will discuss the driving forces, including energy dissipation, speed, area, and technological factors for the projected end‐of‐the roadmap technology. Yet, there continues to be a search for new device technologies to supplement, or replace, Si CMOS. Quantum wires have been sug‐gested in many places as a possible new technology that can provide many opportunities for enhancing chip architecture. But, the constraints on any new technology can be viewed in terms of Si cost, and the manner in which new approaches to devices can be pursued will be dis‐cussed. Some possible technologies are FinFETs, vertical quantum wires, carbon nanotubes, III‐Vs, and similar ap‐proaches. Device downsizing is only one of three driving forces that lead to Moore's Law, with increasing chip size and circuit cleverness playing an equal part. This suggests that many novel devices should not be viewed as competition to CMOS, but in the light of how they may modify the circuit architecture. Indeed, circuit clev‐erness has been as important in managing breakthroughs in the past as new processing technology. Some new op‐portunities, that arise from the nature of nanowire fabri‐cation, in these novel devices may lead to breakthroughs in the area of circuit cleverness. (© 2008 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

An experimental study on substrate coupling in bipolar/BiCMOS technologies

The parasitic influence of the substrate can lead to a significant performance degradation of advanced high-speed and RF circuits. Hence, a careful circuit layout is necessary, and shielding measures such as guard rings must usually be applied. However, this might not be sufficient for high-performance circuits. Moreover, such measures often lead to an increased chip size. Therefore, not only the layout but also the technology itself should be optimized to suppress substrate coupling as much as possible. In this work, different technology-related options such as high-resistivity and SOI substrates, transistor isolation techniques, and shielding methods are investigated. Their influence on substrate coupling is determined up to 50 GHz by measurements of special test structures. The observed behavior is thoroughly explained so that guidelines for technology development and circuit design can be derived. This paper focuses primarily on RF and high-speed ICs fabricated in advanced bipolar or BiCMOS technologies using p/sup -/ substrates, although the results apply also to (RF-)CMOS circuits with such substrate materials.

Effect of initial moisture content and chip size on the bioconversion efficiency of softwood lignocellulosics.

Previous optimization strategies for the bioconversion of lignocellulosics by steam explosion technologies have focused on the effects of temperature, pH, and treatment time, but have not accounted for changes in severity brought about by properties inherent in the starting feedstock. Consequently, this study evaluated the effects of chip properties, feedstock size (40-mesh, 1.5 x 1.5 cm, 5 x 5 cm), and moisture content (12% and 30%) on the overall bioconversion process, and more specifically on the efficacy of removal of recalcitrant lignin from the lignocellulosic substrates following steam explosion. Increasing chip size resulted in an improvement in the solids recovery, with concurrent increases in the water soluble, hemicellulose-derived sugar recovery (7.5%). This increased recovery is a result of a decrease in the "relative severity" of the pretreatment as chip size increases. Additionally, the decreased relative severity minimized the condensation of the recalcitrant residual lignin and therefore increased the efficacy of peroxide fractionation, where a 60% improvement in lignin removal was possible with chips of larger initial size. Similarly, increased initial moisture content reduced the relative severity of the pretreatment, generating improved solids and hemicellulose-derived carbohydrate recovery. Both increased chip size and higher initial moisture content results in a substrate that performs better during peroxide delignification, and consequently enzymatic hydrolysis. Furthermore, a post steam-explosion refining step increased hemicellulose-derived sugar recovery and was most effectively delignified (to as low as 6.5%). The refined substrate could be enzymatically hydrolyzed to very high levels (98%) and relatively fast rates (1.23 g/L/h).

Mechanical reliability in electronic packaging

The dramatic increase in the number of devices and functionality of the latest ultra large scale integration designs have resulted in increasing chip size. Concurrently, to achieve higher circuit board component densities, package dimensions have been shrinking. These two competing trends are leading to ever more rigorous requirements on the mechanical characteristics of the packaging technology. The dominant issue in component level reliability is delamination and cracks initiated at the interface between dissimilar materials. In board level reliability, solder joint reliability is a primary issue. This paper describes the methodology of prediction and the explanation for interfacial delamination, cracks at the top of the interfaces and the edge of corner, and also solder joint reliability. This paper furthermore presents the role of the chip backside contamination affecting interfacial delamination, the surface characterizations and an explanation of the interface chemistry, and the strength of solders with a variety of plating materials for Sn–Ag-based lead free solders.

A bus delay reduction technique considering crosstalk

AbstractRecently, progress in shrinking CMOS process technology and increasing chip size has made interconnect delay a serious problem in deep micron LSI design. The interconnect delay is maximized by the influence of crosstalk when adjacent wires simultaneously switch in opposite transient directions. This paper proposes an on‐chip bus delay reduction technique based on shifting the signal transition timing of adjacent wires. From an equation for the approximate bus delay, delay reduction can be achieved by applying the proposed technique to repeater‐inserted on‐chip buses. The result of SPICE simulation also shows that at most a 20% reduction of the total bus delay can be achieved. © 2001 Scripta Technica, Electron Comm Jpn Pt 3, 85(1): 24–31, 2002

Do chip size limits exist for DCA?

Solder joints, the most widely used flip chip on board (FCOB) interconnects, have a relatively low structural compliance due to the large thermal expansion mismatch between silicon die and the organic substrate. The coefficient of thermal expansion (CTE) of the printed wiring board (PWB) is almost an order of magnitude greater than that of the integrated circuit (IC). Under operating and testing conditions, this mismatch subjects the solder joints to large creep strains and leads to early failure of the solder connections. The reliability of such flip chip structures can be enhanced by applying an epoxy-based underfill between the chip and the substrate, encapsulating the solder joints. This material, once cured, mechanically couples the IC and substrate together to locally constrain the CTE mismatch. However, the effects of CTE mismatch are assumed to become more severe with increasing chip size. Even with the addition of an underfill material, it has been supposed that there are limits on the chip size used in flip chip applications.

An algorithm for determining repetitive patterns in very large IC layouts

This paper proposes an isometry invariant pattern matching algorithm tailored for layout-related processing of complex integrated circuit (IC) designs. This algorithm applies signatures identifying contour equivalence classes. The proposed algorithm is useful for data reduction purposes by enabling construction of a database of repeatable IC primitives. We show several results of analysis of the state-of-the-art IC's which suggest that the diversity of patterns does not significantly increase with increasing chip size.

An ART1 microchip and its use in multi-ART1 systems

Recently, a real-time clustering microchip neural engine based on the ART1 architecture has been reported. However, that chip rendered an extremely high silicon area consumption of 1 cm(2), and consequently an extremely low yield of 6%. Redundant circuit techniques can be introduced to improve yield performance at the cost of further increasing chip size. In this paper we present an improved ART1 chip prototype based on a different approach to implement the most area consuming circuit elements of the first prototype: an array of several thousand current sources which have to match within a precision of around 1%. Such achievement was possible after a careful transistor mismatch characterization of the fabrication process (ES2-1.0 mum CMOS). A new prototype chip has been fabricated which can cluster 50-b input patterns into up to ten categories. The chip has 15 times less area, shows a yield performance of 98%, and presents the same precision and speed than the previous prototype. Due to its higher robustness multichip systems are easily assembled. As a demonstration we show results of a two-chip ART1 system, and of an ARTMAP system made of two ART1 chips and an extra interfacing chip.

Fracture Strength Measurement of Silicon Chips

In this study, a three point bending test is used to determine how the susceptivity of large chips to brittle fracture correlates with chip thickness and backend process quality. Four sets of wafer backend processes, including the commonly used mechanical grinding, were used in this experimental work. In the mechanical grinding process, chip strength was more significantly influenced by the geometry of the machine mark than by the depth of the scratched groove. This experimental result indicates that a limitation exists in the enhancement of the mechanical stability of Si chips by the control of chip thickness because cracks in chips have a tendency to seek out deep scratches rather than typical flaws. Therefore, the mechanical instability associated with increasing chip size should be compensated for by optimization of the backlap process.

Floating gate memories reliability

Besides conventional IC failure mechanisms, the floating gate (FG) device reliability is affected by data retention, characteristic of non-volatile memories, and endurance, typical of electrically erasable arrays. The subjects of this work are EPROM and flash EEPROM, the leading and most promising devices among the FG non-volatile memories. The degradation mechanisms observed in programming and erasing steps are investigated. EPROM data retention is associated with intrinsic and defect related charge loss with both electronic and ionic processes involved. Experimental results are presented. The reliability problems associated with repeated write/erase cycles are introduced, and their effects on EEPROM endurance discussed. Finally, a fishbone diagram for data retention is proposed. The complexity of technology and the cell scaling down with increasing chip size impose lower failure rate goals and reliability becomes integrated within the manufacturing process.

Effect of transient acid diffusion on pretreatment/hydrolysis of hardwood hemicellulose

Diffusivities of sulfuric acid in Aspen wood were experimentally determined at various diffusional temperatures and fitted to Arrhenius equations. These equations were subsequently incorporated into a theoretical model to establish the effect of transient acid concentration gradients within a solid substrate during acid-catalyzed hydrolysis of hemicellulose. Total xylose yield was found to decrease for increasing chip size, and this effect was intensified by increasing reaction temperature. Quantitative criteria were established for assessment of transient acid concentration effects upon xylose yield and reaction time at various reaction conditions.

Effect of transient variation of temperature on acid hydrolysis of aspen hemicellulose

Thermal diffusivities of Aspen wood were experimentally determined and subsequently incorporated into a theoretical model to establish the effect of transient temperature variation within a solid substrate during acid catalyzed hydrolysis of hemicellulose. The simulation results were analyzed to evaluate the impact of particle size on hemicellulose hydrolysis. Total xylose yield was found to decrease for increasing chip size and this effect was intensified by increasing reaction temperature. Quantitative criteria were established for assessment of transient temperature effect on xylose yield and reaction time at various reaction conditions.