Increased Wiring Density Research Articles

Differential signal balancer embedded in silicon LSI as smallest common-mode filter combined bifilar coupling inductors and stacked delay lines

The new differential signal balancer embedded in the metal wiring layer of silicon LSI having increased wiring density and improved characteristics is developed. An internal delay line circuit is stacked vertically to obtain a larger delay time than the extended horizontally structure, and the two inductors for common-mode noise rejection are configured with a stacked bifilar winding structure to obtain higher effective coupling and lower parasitic resistance. Compared to the previous design, the common-mode rejection ratios at 2.4 GHz and 5.4 GHz have been improved by 4.0 dB and 4.6 dB in a smaller area of 120 × 230 μm2, respectively.

Fabrication of Feedhorn-Coupled Transition Edge Sensor Arrays for Measurement of the Cosmic Microwave Background Polarization

Characterization of the minute cosmic microwave background polarization signature requires multi-frequency, high-throughput precision instrument systems. We have previously described the detector fabrication of a 40 GHz focal plane and now describe the fabrication of detector modules for measurement of the CMB at 90 GHz. The 90 GHz detectors are a scaled version of the 40 GHz architecture where, due to smaller size detectors, we have implemented a modular (wafer level) rather than the chip-level architecture. The new fabrication process utilizes the same design rules with the added challenge of increased wiring density to the 74 TES's as well as a new wafer level hybridization procedure. The hexagonally shaped modules are tile-able, and as such, can be used to form the large focal planes required for a space-based CMB polarimeter. The detectors described here will be deployed in two focal planes with 7 modules each in the Johns Hopkins University led ground-based Cosmology Large Angular Scale Surveyor (CLASS) telescope.

Z-Axis Interconnection: A Versatile Technology Solution for High Performance Electronics

This paper presents a novel Z-axis interconnect approach for extending performance beyond the limits imposed by traditional approaches. Specifically, metal-to-metal z-axis electrical interconnection among substrates (subcomposites) of the same or varying size, or among flexible and rigid elements (rigid-flex), to form a single structure is described. The structure employs an electrically conductive medium to interconnect thin coreless substrates. The substrates are built in parallel, aligned, and laminated to form a variety of multilayer high density structures including rigid, rigid-rigid, rigid-flex, stacked packages, or RF substrates. The z-interconnect based structures offer many advantages over more conventional build-up technologies. For example, it enables designs having increased wiring density, leading to greatly reduced layer counts. When an increase in metal layer counts is required, z-interconnect avoids the cumulative yield loss of sequential (build up) processing. The parallel processing of cores and/or subcomposites leads to reduced fabrication cycle time. Avoidance of through hole drilling allows for reduction or elimination of via stubs that cause signal attenuation at high frequencies. In addition, multilayer rigid-flex packages for a variety of applications are being developed. For these applications, z-interconnect allows for placement of flex elements into any layer of the substrate, the opportunity for multiple flex layers within a rigid-flex substrate, the ability to connect multiple multilayer substrates of varying size, and the ability to connect between any two arbitrary metal layers within the rigid region without the use of plated through holes (PTHs). The process allows fabrication of z-interconnect conductive joints having diameters in the range of 55–500 microns. Via or component pitches down to 150 microns have been demonstrated. A number of RF structures have been designed and built with z-interconnect technology, affording the flexibility to place wide signals, narrow signals and grounds and clearances only where needed. Electrically, S-parameter measurements revealed low loss at multi-gigahertz frequencies and the insertion loss for narrow, short lines and wide, long lines are similar. The electrically conductive adhesive used to form z-interconnects shows good signal transmission to 25GHz. Z-interconnect technology provides unique solutions for next generation complex packaging products.

Versatile Z-Axis Interconnection for High Performance Electronics

The demand for high-performance, lightweight, portable computing power for next generation packaging is driving the industry toward miniaturization at a rate not seen before. Electronic packaging is evolving to meet the demands of higher functionality in ever smaller packages. To accomplish this, new packaging needs to be able to integrate more dies with greater function, higher I/O counts, smaller die pad pitches, and greater heat densities, while being pushed into smaller and smaller footprints. New packaging designs are emerging that require joining (stacking) of multiple packages, joining of different size packages, and flexibility and/or rigidity to accommodate requirements related to size, weight, and complexity. This paper presents a novel Z-axis interconnect approach for extending performance beyond the limits imposed by traditional approaches. Specifically, metal-to-metal z-axis electrical interconnection among substrates (sub-composites) of the same or varying size, or among flexible and rigid elements (rigid-flex), to form a single structure is described. The structure employs an electrically conductive medium to interconnect thin coreless substrates. The substrates are built in parallel, aligned, and laminated to form a variety of multilayer, high density structures including rigid, rigid-rigid, rigid-flex, stacked packages, or RF substrates. The Z-interconnect based structures offer many advantages over more conventional build-up technologies, for example, an increase in metal layer counts without the cumulative yield loss of sequential (build up) processing, placement of flex elements into any layer of the substrate, the opportunity for multiple flex layers within a rigid-flex substrate, the ability to connect multiple multilayer substrates of varying size, and the ability to connect between any two arbitrary metal layers within the rigid region without the use of plated through holes (PTHs), allowing for increased wiring density, and reduction or elimination of via stubs that cause signal attenuation, In addition, multilayer rigid-flex packages for a variety of applications are being developed. Several classes of flexible materials that can be used to form high-performance flexible packaging are discussed. Materials, including polyimides, PTFE, liquid crystal polymer (LCP), have been used to develop multilayer rigid-flex packages. The process allows fabrication of Z-interconnect conductive joints having diameters in the range of 55–500 microns. Via or component pitches down to 150 microns have been demonstrated. The processes and materials used to achieve smaller feature dimensions, satisfy stringent registration requirements, and achieve robust electrical interconnections are discussed. A number of RF structures have been designed and built with Z-interconnect technology, affording the flexibility to place wide signals, narrow signals and grounds and clearances only where needed. Electrically, S-parameter measurements revealed low loss at multi-gigahertz frequencies and the insertion loss for narrow, short lines and wide, long lines are similar. The electrically conductive adhesive used to form Z-interconnect shows good signal transmission to 25GHz. Z-interconnect substrates provide unique solutions for next generation complex packaging. Collectively, the results suggest that Z-interconnect technology may be attractive for a range of applications, not only where miniaturization is required, such as consumer products, but also in high performance large-area microelectronics such as supercomputers, radio frequency structures, etc.

Copper electroplating technology for microvia filling

This paper describes a copper electroplating enabling technology for filling microvias. Driven by the need for faster, smaller and higher performance communication and electronic devices, sequential build up (SBU) technology has been adopted as a viable multilayer printed circuit manufacturing technology. Increased wiring density, reduced line widths, smaller through‐holes and microvias are all attributes of these high density interconnect (HDI) packages. Filling the microvias with conductive material allows the use of stacked vias and via in pad designs. Other potential design attributes include thermal management enhancement and benefits for high frequency circuitry. Electrodeposited copper can be utilized for filling microvias and provides potential advantages over alternative via plugging techniques. The features, development, scale up and results of direct current (DC) and periodic pulse reverse (PPR) acid copper via filling processes, including chemistry and equipment, are described.

MCM-D/C packaging solution for IBM latest S/390 servers

The G5, the most recent member of the S390 server family, was announced in May 1998. The multichip module (MCM) at the heart of the G5 system consists of 29 CMOS chips on a 127.5 mm glass ceramic substrate with 6 levels of thin films (TF) including 1 signal plane pair. System performance of the G5 exceeds 1000 MIPS. This breakthrough performance resulted from the synergy created by combining IBM's leadership technologies in CMOS high frequency microprocessor design with advanced packaging and flip chip interconnections. From a substrate perspective. IBM moved from alumina ceramic with molybdenum (Mo) conductor to cordurite/glass ceramic, and copper (Cu) conductor, and from TF redistribution (4 levels) to TF wiring (6 levels). This paper discusses the TF implications from a change of substrate material and increased wiring density, as well as the need to implement a polyimide cushion layer as part of a pin grid array (PGA) fabrication process that supports 4224 I/O's.

Optoelectronic Packaging for Computer and Communication Systems

AbstractThe principal driver behind advanced hardware development in the communications and computer industries can be reduced to an optimal set of parameters related to performance, cost and reliability. High performance systems typically have high functional density. For example, the continuing trend of VLSI is toward reduced feature size, increased wiring density and larger chip size to achieve increasingly higher levels of on-chip functionality. At some point in the cost structure, however, the single chip solution is no longer viable, and monolithic integration gives way to hybrid integration. In this respect, the multichip module fills a void in the packaging/ integration hierarchy between the ever-larger single chip and the printed wiring board.An analogous situation is emerging in optoelectronics. The single chip package with its relatively low system functionality and high cost is giving way to the multi-technology module that integrates optical and electronic functions within a single package. One of the most interesting approaches to the multi-technology module uses a silicon substrate as the platform for hybrid integration of electronics and optoelectronics. It will be argued that this “silicon waferboard” approach is the cost-effective route to manufacturability of high-performance modules for communications and computer systems. Enhanced reliability follows from applying standard IC processing technology at the platform level in the packaging hierarchy.